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can/lin sbc family with dc/dc voltage regulator e521 .02/03/04/12/13/14 production data ? mar 7, 2016 features ? high efficiency 5v dc/dc buck converter ? optional dc/dc boost converter ? wakeable hs-can transceiver (iso11898-2 and -5) ? up to four lin transceiver lin 2.1, sae-j2602 confo rmance ? operating range 2.5v up to 28v ? typ. 45a sleep current consumption ? typ. 85a standby current consumption with active d c/dc buck converter ? configurable c watchdog (cycle time and type) ? bus pins esd-protected 8kv according to iec-61000-4 -2 ? package qfn44l7 with booster without booster no. of lins e521.12 e521.02 2 e521.13 e521.03 3 e521.14 e521.04 4 applications ? body control units, gateways general description the can/lin sbc family with dc/dc voltage reg- ulator provides beside the can and lin tran- ceivers the main c power supply with a high effi- ciency dc/dc converter. an additional linear regu- lator can be used independently as peripheral sup- ply. all supplies are monitored and can signalize a fail event by spi interface. the main dc/dc sup- ply monitor can generate a c reset. system fail- ure can activate a fail-safe output signal for limp home support. the can/lin sbc family provides sleep, stop, active and failsafe states. the device is capable of detecting local and remote wake-up events which can be individually enabled via spi. typical applications circuit elmos semiconductor ag reserves the right to change the detail specifications as may be required to pe rmit improvements in the design of its products. elmos semiconductor ag data sheet qm-no.: 25ds0093e.0 1
can/lin sbc family with dc/dc voltage regulator e521 .02/03/04/12/13/14 production data ? mar 7, 2016 functional diagram elmos semiconductor ag reserves the right to change the detail specifications as may be required to pe rmit improvements in the design of its products. elmos semiconductor ag data sheet qm-no.: 25ds0093e.0 1 2 / 82 wake gnd rstn vdd1sense lxt wk rxdlin1 txdlin1 clk sdi sdo csn intn vdd2 gndlin lin1 canl canh rxdcan txdcan pgnd voltage regulator 5v vddcan fson lin transceiver hs-can transceiver rxdlinx txdlinx linx swdm reset generation vs vs vs optional blocks lin_enx lin transceiver fail safe lowside control mdrv isen pgnd2 en_buk wulinx wucan en_v2 en_bst dc/dc boost converter vs can_en watch dog vs envdd2 dc/dc buck converter vin vdd1 vdd1
can/lin sbc family with dc/dc voltage regulator e521 .02/03/04/12/13/14 production data ? mar 7, 2016 pin configuration note: top view, not to scale pin description pin name type description 1 fson o fail safe output, open drain stage, low activ e 2 rstn io reset output, low active, pull up 3 intn io interrupt output, low active, pull up setup for bit sbc.cfg 4 txdlin4 i lin4 transmit data, pull up, optional e521.04/.14, only all other versions are not connec ted 5 rxdlin4 o lin4 receive data e521.04/.14 only, all other versions are not connec ted 6 vdd1 s voltage supply 1 7 gnd s ground 8 txdlin3 i lin3 transmit data, pull up, optional e521.03/.04/.13/.14 only, all other versions are no t connected elmos semiconductor ag reserves the right to change the detail specifications as may be required to pe rmit improvements in the design of its products. elmos semiconductor ag data sheet qm-no.: 25ds0093e.0 1 3 / 82 ela-0158 1 2 3 4 5 44 43 42 41 40 6 7 8 9 10 11 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 12 13 14 15 16 17 18 19 20 21 22 fson rxdlin1 txdlin1 lin2 lin1 lin4 lin3 sdi sdo sck rxdcan csn mdrv vdd2 pgnd2 isen vs wk n.c. lxt n.c. rstn intn txdlin4 rxdlin4 vdd1 gnd txdlin3 rxdlin3 txdlin2 rxdlin2 pgnd vdd1sense canl canh vddcan gnd vdd1 swdm envdd2 txdcan vin vin gndlin
can/lin sbc family with dc/dc voltage regulator e521 .02/03/04/12/13/14 production data ? mar 7, 2016 pin name type description 9 rxdlin3 o lin3 receive data e521.03/.04/.13/.14 only, all other versions are no t connected 10 txdlin2 i lin2 transmit data, pull up 11 rxdlin2 o lin2 receive data 12 txdlin1 i lin1 transmit data, pull up 13 rxdlin1 o lin1 receive data 14 lin1 io lin1 bus line 15 lin2 io lin2 bus line 16 gnd s lin ground 17 lin3 io lin3 bus line, e521.03/.04/.13/.14 only, all other versions are no t connected 18 lin4 io lin4 bus line, e521.04/.14 only, all other versions are not connec ted 19 csn i spi chip select, low active, pull up 20 sdi i spi serial data input 21 sck i spi clock, pull down 22 sdo o spi serial data output 23 rxdcan o can receive data 24 txdcan i can transmit data, pull up 25 envdd2 i enables vdd2 26 swdm i must be connected to gnd in application enables software development function, pull down 27 gnd s ground 28 vdd1 s voltage supply 1 29 canl io canl bus line 30 canh io canh bus line 31 vddcan s hs-can supply 32 vdd1sense io vdd1 sense back to dcdc buck converter 33 pgnd s dcdc buck converter power ground 34 lxt io dcdc buck converter integrated highside switch output elmos semiconductor ag reserves the right to change the detail specifications as may be required to pe rmit improvements in the design of its products. elmos semiconductor ag data sheet qm-no.: 25ds0093e.0 1 4 / 82
can/lin sbc family with dc/dc voltage regulator e521 .02/03/04/12/13/14 production data ? mar 7, 2016 pin name type description 35 n.c. not connected 36 vin s dcdc supply 37 vin s dcdc supply 38 n.c. not connected, leave open 39 vs s battery supply voltage 40 wk i local wake up input, pull up or pull down 41 pgnd2 s power ground 2 (boost converter), e521.12/.13/.14 only, all other versions are not co nnected 42 isen i sense input (boost converter), e521.12/.13/.14 only, all other versions are not co nnected 43 mdrv o main gate driver output (boost converter), e521.12/.13/.14 only, all other versions are not co nnected 44 vdd2 s peripheral voltage supply - ep s exposed pad. connect to large copper ground plane f or optimal heat dissipa- tion. connect to gnda and gndd. note: s = supply, i/o = input/output elmos semiconductor ag reserves the right to change the detail specifications as may be required to pe rmit improvements in the design of its products. elmos semiconductor ag data sheet qm-no.: 25ds0093e.0 1 5 / 82
can/lin sbc family with dc/dc voltage regulator e521 .02/03/04/12/13/14 production data ? mar 7, 2016 1 absolute maximum ratings stresses beyond these absolute maximum ratings list ed below may cause permanent damage to the device. these are stress ratings only; operation of the device at these or any other condi tions beyond those listed in the operational sectio ns of this document is not implied. exposure to absolute maximum rated conditions for extended periods may affect device reliability. all voltages with respect to ground. currents flowing into terminals are positive, those drawn out of a terminal are negative. description condition symbol min max unit voltage at vs 1) , 2) continuous v vs -0.3 40 v voltage at vin 1) , 2) continuous v vs -0.3 40 v voltage at wk, fson, envdd continuous v wk -0.3 40 v voltage at lin1..4, canl, canl continuous v canl -27 40 v voltage at lxt continuous v lxt -2 v vin + 0.3 v voltage at vddcan continuous v vddcan -0.3 5.5 v voltage at swdm continuous v swdm -0.3 5.5 v voltage at digital pins txdlin1..4, rxdlin1..4, txdcan, rxdcan continuous v txdlin -0.3 v vdd1 +0.3 v voltage at vdd1 continuous v vdd1 -0.3 5.5 v voltage at vdd2 continuous v vdd2 -5 40 v current at wk continuous i wk -15 1 ma current of vdd1 continuous i vdd1 -500 ma current of vdd2, internally limited continuous i vdd2 -200 1 ma current at envdd2 continuous i envdd2 -15 1 ma maximum load at rxdcan c rxdcan,load 10 pf junction temperature continuous t junc -40 150 c storage temperature continuous t stg -55 125 c 1) the device is implicitly protected against load du mp 2) the device is implicitly protected against jump st art elmos semiconductor ag reserves the right to change the detail specifications as may be required to pe rmit improvements in the design of its products. elmos semiconductor ag data sheet qm-no.: 25ds0093e.0 1 6 / 82
can/lin sbc family with dc/dc voltage regulator e521 .02/03/04/12/13/14 production data ? mar 7, 2016 2 esd protection description condition symbol min max unit esd hbm protection pins vdd2, linx, wk, canh and canl 1) v esd(hbm) -8 +8 kv esd hbm protection all other pins 1) v esd(hbm) -2 +2 kv esd system level protection pins vdd2, linx, wk, canh and canl 3) to ground v esd(iec) -6 +6 kv esd cdm protection at all pins 2) v esd(cdm) -500 +500 v esd cdm protection at edge pins 2) v esd(cdm)c -750 +750 v 1) according to aec-q100-002 (hbm) chip level test, c =100pf, r=1.5k 2) according to aec-q100-011 (cdm) chip level test, r =1 2) similar to iec61000-4-2, c=150pf, r=330 3 recommended operating conditions description condition symbol min typ max unit functional range e521.02..04 v vs,func 5.5 - 28 v functional range e521.12..14 v vs,func 2.5 - 28 v limited functional range e521.02..04 v vs,fl,lr 2.5 - 5.5 v limited functional range e521.02..04, e521.12..14 v vs,fl,hr 28 - 40 v ambient temperature t amb -40 - 125 c elmos semiconductor ag reserves the right to change the detail specifications as may be required to pe rmit improvements in the design of its products. elmos semiconductor ag data sheet qm-no.: 25ds0093e.0 1 7 / 82
can/lin sbc family with dc/dc voltage regulator e521 .02/03/04/12/13/14 production data ? mar 7, 2016 4 electrical characteristics (v vs = 5.5v to 28v, t amb = -40c to +125c, unless otherwise noted. typical values are at v vs = 12.0v and t amb = +25c. positive currents flow into the device pins.) 4.1 power supply and references; pins vs, gnd no. description condition symbol min typ max unit 1 current consumption in sbc mode sleep 1) sbc mode sleep, v s = v lin = v wk = 13.5v, i vdd1 = 0ma, i vdd2 = 0ma, t j <40c, booster is off all wake up sources enabled i vs,sleep 45 110 a 1a current consumption in sbc mode sleep 1) sbc mode sleep, v s = v lin = v wk = 13.5v, i vdd1 = 0ma, i vdd2 = 0ma, t j >40c, booster is off all wake up sources enabled i vs,sleep,40 65 150 a 2 current share for can wake up capability in sbc mode sleep v s = 13.5v not production tested i vs,can,sleep 5 10 a 3 current share for lin wake up capability in sbc mode sleep v s = 13.5v not production tested i vs,lin,sleep 2 5 a table 1: dc characteristics sleep 1) not production tested elmos semiconductor ag reserves the right to change the detail specifications as may be required to pe rmit improvements in the design of its products. elmos semiconductor ag data sheet qm-no.: 25ds0093e.0 1 8 / 82
can/lin sbc family with dc/dc voltage regulator e521 .02/03/04/12/13/14 production data ? mar 7, 2016 no. description condition symbol min typ max unit 1 current consumption in sbc mode stop without booster sbc mode stop, v vs = v lin = v wk = 13.5v, i vdd1 = 0ma, can off, lin off, vdd2 off, all wake up sources enabled, t j >40 i vs,stb,t<=125c 100 170 a 1a current consumption in sbc mode stop without booster sbc mode stop, v vs = v lin = v wk = 13.5v, i vdd1 = 0ma, can off, lin off, vdd2 off, all wake up sources enabled, t j <40 i vs,stb,t<=40c 85 140 a 2 additional current if vdd2 has load v vs = 13.5v, i vdd2 = -40ma i vs,vdd2 0.1*i vdd2 ma 3 current consumption of vdd2 voltage regulator in case of low load of 0.2ma 1) v vs = 13.5v, i vdd2 = -0.2ma i vs,vdd2,0.2ma 1 ma 4 additional current in sbc mode stop if cyclic wake up enabled 1) stop mode, v vs = v lin = v wk = 13.5v, cyclic wake up enabled i vs,stb,cyclic 10 a table 2: dc characteristics stop no. description condition symbol min typ max unit 1 normal mode current consumption i vs,nom 150 400 a 2 current consumption in active mode for all lins not production tested lin dominant i vs,lin,act,dom 1.5 3 ma 3 current consumption in active mode for all lins lin recessive i vs,lin,act,rec 0.25 0.5 ma 4 current consumption in active mode for can can recessive i vddcan,can,act,rec 1 3 ma 5 current consumption in active mode for can not production tested can dominant i vddcan,can,act,dom 40 105 ma table 3: dc characteristics normal 1) not production tested elmos semiconductor ag reserves the right to change the detail specifications as may be required to pe rmit improvements in the design of its products. elmos semiconductor ag data sheet qm-no.: 25ds0093e.0 1 9 / 82
can/lin sbc family with dc/dc voltage regulator e521 .02/03/04/12/13/14 production data ? mar 7, 2016 no. description condition symbol min typ max unit 1 power on threshold according to pin vs v vs,pu 4 5 v 2 power down threshold according to pin vs v vs,pd 2.0 2.5 v table 4: dc characteristics por 4.1.1 internal time base no. description condition symbol min typ max unit 1 internal time base, started auto- matically on demand. most times specified are derived from this internal time base directly or by using prescalers. t osc 0.875 1.125 s table 5: ac characteristics 4.2 sbc operating modes no. description condition symbol min typ max unit 1 time out in sbc states init and restart t to,init 230 256 290 ms 2 time out in sbc states init and restart for vdd1 start up vs rises above v on- off,vs in before and not fallen below v on-off_f,vs t to,vdd1 1.4 1.5 1.8 s 3 duration for changes between sbc states detection of vaild state change condi- tion t mode_change 8 s 4 vs voltage threshold to be exceeded in order to start timeout t to,vdd1 1) v on-off,vs 6.3 6.6 6.9 v 5 vs voltage threshold to be under- flow in order to deactivate timeout t to,vdd1 1) v on-off_f,vs 5.75 6.05 6.35 v table 6: ac characteristics 1) hysteresis is designed to 550mv, not production te sted elmos semiconductor ag reserves the right to change the detail specifications as may be required to pe rmit improvements in the design of its products. elmos semiconductor ag data sheet qm-no.: 25ds0093e.0 1 10 / 82
can/lin sbc family with dc/dc voltage regulator e521 .02/03/04/12/13/14 production data ? mar 7, 2016 vdd1 current observation in stop mode no. description condition symbol min typ max unit 1 timeout for whole system to enter stop mode and therefore to decrease current consumption spi command for stop mode sent t tran_stop 2.3 2.6 3.2 ms 2 threshold for vdd1 observation, 5v system. upper limit ensures a safe voltage difference to vdd1 of 50mv using production test data for each particular ic. sbc mode stop k1 vdd1,5v 4.625 v vdd1 - 50mv v 3 minimum time vdd1 needs to stay above k1 vdd1 after this time dcdc is switched on for ton_reg,stop in order to recharge vdd1 vdd1_cfg[7:6]= 0h t1 0 4.7 6.4 ms 4 minimum time vdd1 needs to stay above k1 vdd1 after this time dcdc is switched on for t on_reg,stop p in order to recharge vdd1 vdd1_cfg[7:6]= 1h (default) t1 1 9.7 12.4 ms 5 minimum time vdd1 needs to stay above k1 vdd1 after this time dcdc is switched on for ton_reg,stop in order to recharge vdd1 vdd1_cfg[7:6]= 2h t1 2 19.5 24.5 ms 6 minimum time vdd1 needs to stay above k1 vdd1 after this time dcdc is switched on for ton_reg,stop in order to recharge vdd1 vdd1_cfg[7:6]= 3h t1 3 39.5 48.6 ms 7 on time of dcdc during regular recharge phase stop mode t on_reg,stop 110 160 s 8 internal delay of dcdc after switching on request t del,on - 10 25 s table 7: characteristics elmos semiconductor ag reserves the right to change the detail specifications as may be required to pe rmit improvements in the design of its products. elmos semiconductor ag data sheet qm-no.: 25ds0093e.0 1 11 / 82
can/lin sbc family with dc/dc voltage regulator e521 .02/03/04/12/13/14 production data ? mar 7, 2016 4.2.1 configuration for transition behaviour to sta tes failsafe or restart no. description condition symbol min typ max unit 1 pull down resistance active during determination phase for sbc_cfg.cfg sbc state init r intn,sbc_cfg.cfg,pd 80 105 150 k 2 voltage level for detecting logic level low at intn sbc state init v intn,sbc_cfg,l 0.7 v 3 voltage level for detecting logic level high at intn sbc state init v intn,sbc_cfg,h 2.6 v table 8: dc characteristics software development function; pin swdm no. description condition symbol min typ max unit 1 voltage to be applied to pin swdm in order to enable software development function v enable,swdm 0.7 vdd1 2 pull down resistance r pd,swdm 80 120 200 k table 9: dc characteristics over temperature behaviour no. description condition symbol min typ max unit 1 can over temperature detected can enabled t ot,can 150 c 2 lin over temperature detected. each lin has its own sensor. lin enabled t ot,lin 150 c 3 vdd1 over temperature detected 1) vdd1 enabled t ot,vdd1 150 165 c 4 vdd1 over temperature detection hysteresis 1) vdd1 enabled t ot,vdd1,hyst 40 c 5 vdd2 over temperature warning detected vdd2 enabled t ot,vdd2,warn 120 c 6 temperature difference between failure and warning threshold vdd2 enabled t ot,vdd2,fail to warn 10 c 7 vdd2 over temperature detected vdd2 enabled t ot,vdd2,fail 140 180 c 8 over temperature for aux. internal structures detected system in state normal t ot,int 140 c 9 over temperature detection hys- teresis, valid for all sensors except otherwise stated 1) temperature sensor enabled t ot,hyst 20 c table 10: ot characteristics 1) not production tested elmos semiconductor ag reserves the right to change the detail specifications as may be required to pe rmit improvements in the design of its products. elmos semiconductor ag data sheet qm-no.: 25ds0093e.0 1 12 / 82
can/lin sbc family with dc/dc voltage regulator e521 .02/03/04/12/13/14 production data ? mar 7, 2016 spi communication; pins sck, sdi, sdo, csn no. description condition symbol min typ max unit 1 high level input voltage v csn,inh 0.7 vdd1 2 low level input voltage v csn,inl 0.3 vdd1 3 high level input current v csn = v vdd1 i csn,leak -1 0 1 a 4 pull up resistor v csn = 0v r csn,pu 120 k 5 high level input voltage v sck,inh 0.7 vdd1 6 low level input voltage v sck,inl 0.3 vdd1 7 pull down resistor v sck = v vdd1 r sck,pd 120 k 8 high level input voltage v sdi,inh 0.7 vdd1 9 low level input voltage v sdi,inl 0.3 vdd1 10 low level output voltage i sdo = 1ma v sdo,outl 0.4 v 11 high level output voltage i sdo = -1ma v sdo,outh v vdd1 - 0.4 v table 11: dc characteristics elmos semiconductor ag reserves the right to change the detail specifications as may be required to pe rmit improvements in the design of its products. elmos semiconductor ag data sheet qm-no.: 25ds0093e.0 1 13 / 82
can/lin sbc family with dc/dc voltage regulator e521 .02/03/04/12/13/14 production data ? mar 7, 2016 no. description condition symbol min typ max unit 1 serial clock cycle (1) sck t scyc 125 ns 2 sck "h" pulse width (1) sck t shw 50 ns 3 sck "l" pulse width (1) sck t slw 50 ns 4 data setup time (wr) (1) sdi t sds 50 ns 5 data hold time (1) sdi t sdh 50 ns 6 access time (1) sdo t acc 50 ns 7 output enable time (1) sdo t oe 50 ns 8 output disable time (1) sdo t od 50 ns 9 sck-csn (1) csn t scc 50 ns 10 csn "h" pulse (1) minimum time between two con- secutive spi accesses csn t chw 5 us 11 csn-sck time (1) csn t css 125 ns 12 output disable time (1) csn t csh 120 ns table 12: ac characteristics (1) not production tested 4.3 watchdog; pin rstn no. description condition symbol min typ max unit 1 minimum watchdog time base important for safe trigger area t wd,per,min 0.85 t wd,per 2 maximum watchdog time base important for safe trigger area t wd,per,max 1.15 t wd,per 3 first open window open window after rstn is released t wd,fow 230 290 ms 4 watchdog reset time t wd,rstn 450 650 s table 13: ac characteristics elmos semiconductor ag reserves the right to change the detail specifications as may be required to pe rmit improvements in the design of its products. elmos semiconductor ag data sheet qm-no.: 25ds0093e.0 1 14 / 82
can/lin sbc family with dc/dc voltage regulator e521 .02/03/04/12/13/14 production data ? mar 7, 2016 4.3.1 external reset / reset clamping no. description condition symbol min typ max unit 1 output low level i rstn = 1ma v vdd1 > 3v v rstn,outl 0.4 v 2 internal pull up resistor v rstn = 0v r rstn,pu 22 32 42 k 3 voltage level for detecting low at rstn v rstn,inl 0.7 v 4 voltage level for detecting high at rstn v rstn,inh 2.6 v table 14: dc characteristics no. description condition symbol min typ max unit 1 debounce time for external applied reset t rstn,deb 4 ms 2 time out for short detection to vdd1 t rstn,to,vdd 16 ms 3 time out for short detection to gnd , can only be detected after t wd,rstn or t vdd1,rstn t wdrstn,to,gnd 16 ms table 15: ac characteristics 4.4 local wake up; pin wk no. description condition symbol min typ max unit 1 threshold of local wake up, v wk rising v wk rising v wk,th,lh 0.6 0.8 vs 2 threshold of local wake up, v wk falling v wk falling v wk,th,hl 0.5 0.7 vs 3 pull up current v wk > v wk,th,lh_max vs - v wk > 1v i wk,pu -100 -10 a 4 pull down current v wk < v wk,th,hl_min v wk > 1v i wk_pd 10 100 a 5 leakage current vs = 12v, v wk = 0v or v wk = v vs i wk_leak -2 +2 a table 16: dc characteristics no. description condition symbol min typ max unit 1 local wake up debounce time threshold crossing transition detected t wk,deb 20 30 s table 17: ac characteristics elmos semiconductor ag reserves the right to change the detail specifications as may be required to pe rmit improvements in the design of its products. elmos semiconductor ag data sheet qm-no.: 25ds0093e.0 1 15 / 82
can/lin sbc family with dc/dc voltage regulator e521 .02/03/04/12/13/14 production data ? mar 7, 2016 4.5 lin transceiver; pins lin1 to lin4, txdlin1 to txdlin4, rxdlin1 to rxdlin4, gnd- lin 4.5.1 characteristics no. description condition symbol min typ max unit 1 functional range lin transceiver v lin,vs 7 - 18 v 2 recessive output voltage txdlinx = 1 v lin,rec v vs -1v - v vs - 3 dominant output voltage txd = 0, v vs = 7.0v, r lin = 0.5k to v vs v lin,dom - - 1.2 v 4 dominant output voltage txdlinx = 0, v vs = 18v, r lin = 0.5k to v vs v lin,dom1 - - 2.0 v 5 receiver dominant level v lin,thdom - - 0.4 vs 6 receiver recessive level v lin,threc 0.6 - - vs 7 lin bus center voltage v linx,buscnt = (v linx,thdom + v linx,threc ) / 2 v lin,buscnt 0.475 - 0.525 vs 8 receiver hysteresis v linx,threc - v lin,thdom v lin,hys 0.02 - 0.175 vs 9 output current limitation v linx = v vs,max = 18v i lin,lim 40 - 200 ma 10 pull up resistance r lin,slave 20 33 60 k 11 leakage current flowing into pin lin transmitter passive, 7v < v vs < 18v, 7v < v linx < 18v, v linx > v vs i lin,busrec - - 20 a 12 pull up current flowing out of pin lin transmitter passive, 7v < v vs < 18v, v linx = 0v i lin,busdom -1 - - ma 13 leakage current, ground discon- nected ( gnd device = vs ) v vs = 13.5v, 0v < v linx < 18v i lin,nognd -1 - 0.1 ma 14 leakage current, supply disconnec- ted v vs = 0v, 0v < v linx < 18v i lin - - 20 a 15 leakage current, supply disconnec- ted, t j = 85c, not production tested v vs = 0v, 0v < v linx < 18v i lin,85 - - 15 a 16 clamping voltage, not production tested v vs = 0v, i linx = 1ma v lin,clamp 40 - v table 18: dc characteristics elmos semiconductor ag reserves the right to change the detail specifications as may be required to pe rmit improvements in the design of its products. elmos semiconductor ag data sheet qm-no.: 25ds0093e.0 1 16 / 82
can/lin sbc family with dc/dc voltage regulator e521 .02/03/04/12/13/14 production data ? mar 7, 2016 no. description condition symbol min typ max unit 1 input capacitance, not production tested! 7v < v vs < 18v c lin,pin - - 30 pf 2a receive propagation delay t rxd,pdr ,t rxd,pdf - - 6 s 2b receive propagation delay in flash mode 1) t rxd,pdr,flash , t rxd,pdf,flash - - 2.5 s 3 receive propagation delay sym- metry t rxd,sym -2 - 2 s 4 wake up debounce time t lin,wu 70 150 s 5 duty cycle 1 1) v lin,threc (max) = 0.744*v vs , v lin,thdom (max) = 0.581*v vs , v vs = 7- 18v, t bit = 50us, d lin,1 = t busrec (min)/ (2*t bit ) d lin,1 0.396 - - - 6 duty cycle 2 1) v lin,threc (min) = 0.422*v vs , v lin,thdom (min) = 0.284*v vs , v vs = 7- 18v, t bit = 50us, d lin,2 = t bus- rec (max)/(2*t bit ) d lin,2 - - 0.581 - 7 duty cycle 3 1) v ,lin,threc (max) = 0.778*v vs , v lin,thdom (max) = 0.616*v vs , v vs = 7- 18v, t bit = 96us, d lin,3 = t busrec (min)/ (2*t bit ) d lin,3 0.417 - - - 8 duty cycle 4 1) v lin,threc (min) = 0.389*v vs , v lin,thdom (min) = 0.251*v vs , v vs = 7- 18v, t bit = 96us, d lin,4 = t bus- rec (max)/(2*t bit ) d lin,4 - - 0.590 - 9 receive data baud rate 2) flash mode, v vs = 13v b lin,rxd 250 kbd/s 10 transmit data baud rate 2) flash mode,c lin = 200pf, r lin = 0.5k v vs = 13v b lin,txd 125 kbd/s table 19: ac characteristics 1) bus load conditions (c lin ,r lin ): 1nf, 1k or 6.8nf, 660 or 10nf, 500 2) not production tested elmos semiconductor ag reserves the right to change the detail specifications as may be required to pe rmit improvements in the design of its products. elmos semiconductor ag data sheet qm-no.: 25ds0093e.0 1 17 / 82
can/lin sbc family with dc/dc voltage regulator e521 .02/03/04/12/13/14 production data ? mar 7, 2016 4.5.2 lin txd/rxd no. description condition symbol min typ max unit 1 output low level range i rxd,linx = 1ma v rxd,linx,outl - - 0.4 v 2 output high level range i rxd,linx = -1ma v rxd,linx,outh v vdd1 - 0.4 - - v 3 input low voltage range v txd,linx,inl - - 0.3 vdd1 4 input high voltage range v txd,linx,inh 0.7 - - vdd1 5 internal txd pull up resistor v txd,linx = 0v r txd,linx,pu 80 110 150 k table 20: dc characteristics 4.5.3 lin failure detection and recovery no. description condition symbol min typ max unit 1 time out for txd dominant clamping failure t lin,txd,dom 8.5 12.5 ms 2 time out for lin dominant clamp- ing failure t lin,bus,dom 8.5 12.5 ms table 21: ac characteristics elmos semiconductor ag reserves the right to change the detail specifications as may be required to pe rmit improvements in the design of its products. elmos semiconductor ag data sheet qm-no.: 25ds0093e.0 1 18 / 82
can/lin sbc family with dc/dc voltage regulator e521 .02/03/04/12/13/14 production data ? mar 7, 2016 hs-can transceiver; pins canh, canl, rxdcan, txdcan , vddcan (v vs = 5.5v to 28v, t amb = -40c to +125c, v can =-12v to +12v unless otherwise noted. typical value s are at v vs = 12.0v and t amb = +25c. positive currents flow into the device pins.) no. description condition symbol min typ max unit 1 canh dominant output voltage v txdcan = 0v r l = 50 to 65 v dom_out_h 3.0 4.5 v 2 canl dominant output voltage v txdcan = 0v r l = 50 to 65 v dom_out_l 0.5 2.0 v 3 matching of dominant output voltages (v vddcan - (v canh + v canl )) v txdcan = 0v r l = 50 to 65 v dom_out_match -400 400 mv 4 differential bus dominant output voltages (v canh -v canl ) v txdcan = 0v r l = 50 to 65 v diff_out_dom 1.5 3.0 v 5 recessive output voltage on canh and canl v txdcan = v vdd1 can normal and listen mode v rec_out 2.0 v vddcan / 2 3.0 v 6 differential receiver threshold voltage can normal and listen mode v diff_th 500 700 900 mv 7 differential receiver threshold voltage, can off and wake up detection capability enabled can off, wakeable v diff_th_off 400 1150 mv 8 differential receiver hysteresis voltage can normal and listen mode v diff_hyst 60 mv 9 differential bus recessive output voltages (v canh - v canl ) can recessive, no load v rec_out_off -100 50 mv 9a recessive output voltage at canh and canl, low power mode can recessive, no load v rec,lp -100 100 mv 10 short circuit output current on canl v txdcan = 0v v canl = 40v i sc_out_canl 40 100 ma 11 short circuit output current on canh v txdcan = 0v v canh = -5v i sc_out_canh -100 -40 ma 12 recessive bus current v txdcan = v vdd1 -27v < v canh/l < 32v i rec_out -5 5 ma 13 input leakage current on canl and canh vdd connected to gnd with r = 0 and r = 47k v canh = v canl = 5v i leak_in -10 10 a 14 common mode input resistance r i_com 15 35 k 15 differential input resistance r i_dif 30 70 k 15a common mode input capacitance not production tested v txdcan = vdd1 c i_com 20 pf 15b differential input capacitance not production tested v txdcan = vdd1 c i_dif 10 pf 15c internal r in resistor matching of canh and canl r in_matching -3 3 % elmos semiconductor ag reserves the right to change the detail specifications as may be required to pe rmit improvements in the design of its products. elmos semiconductor ag data sheet qm-no.: 25ds0093e.0 1 19 / 82
can/lin sbc family with dc/dc voltage regulator e521 .02/03/04/12/13/14 production data ? mar 7, 2016 no. description condition symbol min typ max unit 16 differential bus recessive output voltages (v canh - v canl ) v txdcan = vdd1 v diff_out_rec_load -5 5 mv 17 vddcan monitor threshold hs-can enabled v vddcan,uv 4.2 4.6 v 18 vddcan monitor threshold hys- teresis hs-can enabled v vddcan,uv,hyst 100 mv 19 canh / canl common mode voltage range v can -12 12 v table 22: dc characteristics no. description condition symbol min typ max unit 1 data rate range to be transmitted and received can normal or listen mode dr can 40 1000 kbit/s 2 delay txdcan to bus dominant not production tested can normal mode t can,d_txd_bus(dom) 25 110 ns 3 delay txdcan to bus recessive not production tested can normal mode t can,d_txd_bus(rec) 10 95 ns 4 delay bus to rxdcan dominant not production tested can normal or listen mode t can,d_bus_rxd(dom) 15 115 ns 5 delay bus to rxdcan recessive not production tested can normal or listen mode t can,d_bus_rxd(rec) 35 160 ns 6 propagation delay txdcan to rxdcan can normal mode t can,pd_txd_rxd 40 255 ns 7 dominant time for wake up via bus can off, wake up capability enabled, vs = 12v t can,wake_bus_dom 0.75 5 s 8 recessive time for wake up via bus can off, wake up capability enabled, vs = 12v t can,wake_bus_rec 0.75 5 s 9 wake up time out can_cfg.rc = 0, can_cfg.wu = 1 t can,wake2 0.5 2 ms 10 can activation time can_cfg.rc = 1 t can,active 50 s table 23: ac characteristics elmos semiconductor ag reserves the right to change the detail specifications as may be required to pe rmit improvements in the design of its products. elmos semiconductor ag data sheet qm-no.: 25ds0093e.0 1 20 / 82
can/lin sbc family with dc/dc voltage regulator e521 .02/03/04/12/13/14 production data ? mar 7, 2016 4.5.4 txdcan and rxdcan no. description condition symbol min typ max unit 1 output low level range i rxdcan = 1ma v rxd,can,outl - - 0.4 v 2 output high level range i rxdcan = -1ma v rxd,can,outh v vdd1 - 0.4 - - v 3 input low voltage range v txd,can,inl - - 0.3 vdd1 4 input high voltage range v txd,can,inh 0.7 - - vdd1 5 internal txdcan pull up resistor v txdcan = 0v r txd,can,pu 80 110 150 k table 24: dc characteristics 4.5.5 can failure detection and recovery no. description condition symbol min typ max unit 1 time out for txd dominant clamp- ing failure t can,txd,dom 1.4 1.9 ms 2 time out for bus dominant clamp- ing failure t can,bus,dom 1.4 1.9 ms 3 duration of bus dominant or recessive time for can bus failure detection t bus,fail 6 s table 25: ac characteristics 4.6 limp home support; pin fson no. description condition symbol min typ max unit 1 output low level i fson = 1ma v vs > v vs,pd v fson,outl 0.4 v table 26: dc characteristics 4.7 interrupt; pin intn no. description condition symbol min typ max unit 1 output low level i intn = 1ma v vdd1 > 3v v intn,outl 0.4 v 2 pull up resistor v intn = 0v r intn,pu 80 105 150 k table 27: dc characteristics no. description condition symbol min typ max unit 1 calculation time for interrupt related state change condition detected interrupt state change condition detected t intn,setup 8 t osc table 28: ac characteristics elmos semiconductor ag reserves the right to change the detail specifications as may be required to pe rmit improvements in the design of its products. elmos semiconductor ag data sheet qm-no.: 25ds0093e.0 1 21 / 82
can/lin sbc family with dc/dc voltage regulator e521 .02/03/04/12/13/14 production data ? mar 7, 2016 4.8 dcdc buck converter; pins vin, vdd1, vdd1sense, lxt, pgnd no. description condition symbol min typ max unit 1 vdd1 output voltage if enabled, e521.02..04, e521.12..14 i vdd1 = -500ma, c vdd1 > 22 f, esr < 120m , v vin > 5.5v v vdd1,5v 4.9 5.1 v 2 quiescent current consumption of dcdc buck converter in case of switched off, e.g. in sbc mode sleep v vin = 13.5v dcdc off i vin,dcdc_off 9 20 a 3 quiescent current consumption of dcdc buck converter in case of switched on, e.g. in sbc mode normal v vin = 13.5v dcdc on duty cycle = 0% i vin,dcdc_on 160 a 4 reset threshold 1 for vdd1 e521.02..04, e521.12..14 1) vdd1_cfg.thr_ 1:thr_0 = 0h, vdd1 falling v th1,vdd1,rstn 4.4 4.6 v 5 reset release threshold 1 for vdd1 e521.02..04, e521.12..14 1) vdd1_cfg.thr_ 1:thr_0 = 0h, vdd1 rising v th1,vdd1_r,rstn 4.6 4.9 v 6 reset threshold 2 for vdd1 e521.02..04, e521.12..14 1) vdd1_cfg.thr_ 1:thr_0 = 1h, vdd1 falling v th2,vdd1,rstn 3.8 4 v 7 reset release threshold 2 for vdd1 e521.02..04, e521.12..14 1) vdd1_cfg.thr_ 1:thr_0 = 1h, vdd1 rising v th2,vdd1_r,rstn 4.0 4.25 v 8 reset threshold 3 for vdd1 e521.02..04, e521.12..14 1) vdd1_cfg.thr_ 1:thr_0 = 2h, vdd1 falling v th3,vdd1,rstn 3.4 3.6 v 9 reset release threshold 3 for vdd1 e521.02..04, e521.12..14 1) vdd1_cfg.thr_ 1:thr_0 = 2h, vdd1 rising v th3,vdd1_r,rstn 3.6 3.85 v 10 reset threshold 4 for vdd1 e521.02..04, e521.12..14 1) vdd1_cfg.thr_ 1:thr_0 = 3h, vdd1 falling, default selection v th4,vdd1,rstn 3 3.2 v 11 reset release threshold 4 for vdd1 e521.02..04, e521.12..14 1) vdd1_cfg.thr_ 1:thr_0 = 3h, vdd1 rising v th4,vdd1_r,rstn 3.2 3.45 v 12 lxt internal over current protec- tion limit v vin > 5.5v i lxt 650 800 1100 ma 1) hysteresis of reset thresholds is designed to > 15 0mv in 5v system table 29: dc characteristics elmos semiconductor ag reserves the right to change the detail specifications as may be required to pe rmit improvements in the design of its products. elmos semiconductor ag data sheet qm-no.: 25ds0093e.0 1 22 / 82
can/lin sbc family with dc/dc voltage regulator e521 .02/03/04/12/13/14 production data ? mar 7, 2016 no. description condition symbol min typ max unit 1 reset delay time after release of vdd1 reset t rstn,vdd1 4.5 6.5 ms 2 vdd1 under voltage debounce time t deb,vdd1 10 50 s 3 reset reaction time in case of under voltage condition t rr,vdd1,rstn 14 20 s table 30: ac characteristics 4.8.1 pulse frequency modulated (pfm) converter pfm control logic no. description condition symbol min typ max unit 1 switch minimum on time no over current detected t on,min 260 ns 2 minimum on time over current detec- ted t on,oc 100 ns 3 minimum off time without over current t off,min,nom 520 ns 4 nominal minimum off time after over current detection t off,oc,nom 1330 ns 5 extended minimum off time after over currrent detection t off,oc,ext 2450 ns 6 operation frequency depending on ratio v vin /v dd1 and load conditions f op 0 1.7 mhz 7 peak operation frequency f op,max 0.9 1.3 1.7 mhz table 31: ac characteristics elmos semiconductor ag reserves the right to change the detail specifications as may be required to pe rmit improvements in the design of its products. elmos semiconductor ag data sheet qm-no.: 25ds0093e.0 1 23 / 82
can/lin sbc family with dc/dc voltage regulator e521 .02/03/04/12/13/14 production data ? mar 7, 2016 low drop regulator; pins vdd2, envdd2 no. description condition symbol min typ max unit 1 parameter removed 2 output voltage range vdd2 enabled, 6v < v vs < 28v, i vdd2 > -100ma v vdd2,100ma 4.9 5.0 5.1 v 3 output current limitation v vdd2 = 0v, v vs = 28v i vdd2,lim -220 -110 ma 4 information only, rds of regulator for v vs = 5.5v vdd2 enabled, determined for v vs = 5.5v not production tested rds vdd2,vs=5.5v 12 5 information only, rds of regulator for v vs = 5.0v vdd2 enabled, determined for v vs = 5.0v not production tested rds vdd2,vs=5.0v 13 6 information only, rds of regulator for v vs = 4.5v vdd2 enabled, determined for v vs = 4.5v not production tested rds vdd2,vs=4.5v 15 7 information only, rds of regulator for v vs = 4.0v vdd2 enabled, determined for v vs = 4.0v not production tested rds vdd2,vs=4.0v 17 8 information only, rds of regulator for v vs = 3.5v vdd2 enabled, determined for v vs = 3.5v not production tested rds vdd2,vs=3.5v 21 9 under voltage threshold falling vdd2 enabled v uv,thr 4.5 4.8 v 10 under voltage hysteresis vdd2 enabled v uv,hys 100 mv 11 threshold of envdd2 rising v envdd2 rising v envdd2,lh 0.6 0.8 vs 12 threshold of envdd2 falling v envdd2 falling v envdd2,hl 0.5 0.7 vs table 32: dc characteristics elmos semiconductor ag reserves the right to change the detail specifications as may be required to pe rmit improvements in the design of its products. elmos semiconductor ag data sheet qm-no.: 25ds0093e.0 1 24 / 82
can/lin sbc family with dc/dc voltage regulator e521 .02/03/04/12/13/14 production data ? mar 7, 2016 no. description condition symbol min typ max unit 1 under voltage debounce time t deb,uv 150 280 s table 33: ac characteristics 4.9 dcdc boost converter; pins mdrv, isen, pgnd2 no. description condition symbol min typ max unit 1 vs activation and output voltage e521.12, .13, .14 only v vdd1 > tbd. v boost 6.0 6.5 7.0 v 2 current sense threshold e521.12, .13, .14 only v isen 85 100 110 mv 3 current sense input current e521.12, .13, .14 only booster disabled i isen -1 1 a 4 minimum booster input voltage to guarantee defined booster output voltage e521.12, .13, .14 only i load_vs < 600ma v booster_input_min 3.25 v 5 minimum booster input voltage to guarantee defined booster output voltage, current limited to lower value of than defined for v bat_min e521.12, .13, .14 only i load_vs < tbd. v booster_input_min_2 2.5 v 6 internal parasitic resistance of the booster-inductance e521.12, .13, .14 only rdc_l boost 30 m 7 pullup current at isense-pin dur- ing booster is on e521.12, .13, .14 only booster enabled r isense 2 5 a table 34: dc characteristics no. description condition symbol min typ max unit 1 minimum switch off-time t offmin4 0.47 s 2 maximum switch on-time t onmax4 8.4 s 3 minimum switch on-time t onmin4 150 ns table 35: ac characteristics elmos semiconductor ag reserves the right to change the detail specifications as may be required to pe rmit improvements in the design of its products. elmos semiconductor ag data sheet qm-no.: 25ds0093e.0 1 25 / 82
can/lin sbc family with dc/dc voltage regulator e521 .02/03/04/12/13/14 production data ? mar 7, 2016 5 functional description 5.1 power supply and references; pins vs, gnd fig. 1: operating range limitations 5.1.1 internal time base most times specified are derived from internal 1 s t ime base e.g. directly or by using prescalers based on this time base. elmos semiconductor ag reserves the right to change the detail specifications as may be required to pe rmit improvements in the design of its products. elmos semiconductor ag data sheet qm-no.: 25ds0093e.0 1 26 / 82
can/lin sbc family with dc/dc voltage regulator e521 .02/03/04/12/13/14 production data ? mar 7, 2016 5.2 sbc operating modes the device provides the following states: ? off ? init ? normal ? stop ? sleep ? restart ? failsafe transition between states is performed at the lates t t state_change after valid condition detected. fig. 2: sbc state diagram *) watchdog and cyclic wake up use one timer. it is possible to use one at the same time only. a chang e between cyclic wake up and watchdog does not reset timer. elmos semiconductor ag reserves the right to change the detail specifications as may be required to pe rmit improvements in the design of its products. elmos semiconductor ag data sheet qm-no.: 25ds0093e.0 1 27 / 82
can/lin sbc family with dc/dc voltage regulator e521 .02/03/04/12/13/14 production data ? mar 7, 2016 register name address description sbc_cfg 0x01 sbc configuration register. wu_src 0x04 wake up source register. wake up source i s cleared if register is read via spi. spi_fail 0x05 spi programming failure register. regis ter is cleared by reading via spi. vdd_stat 0x1a vdd1, vdd2 and vddcan status informatio n. table 36: registertable register sbc_cfg (0x01) msb lsb content clamp - boost fson cfg state2 state1 state0 reset value 0 0 0 0 0 0 0 0 access r r r/w r r/w r/w r/w r/w bit description clamp : 1.. external reset shorter than t wdrstn,to,gnd will not lead to fson set 0.. external reset leads to fson set immediately info: bit can be written in register fson_cfgx. boost : 1.. enable booster for low voltage at pin vs 0.. do not enable booster for low voltage at pin vs fson : 1.. fson is active 0.. fson is not active cfg : sbc state transition in case of watchdog failure 0.. failsafe 1.. restart state2 ... state0 000.. off 001.. init (cannot be set by spi) 010.. normal 011.. stop 100.. restart 101.. failsafe 110.. sleep 111.. reserved table 37: sbc configuration register. elmos semiconductor ag reserves the right to change the detail specifications as may be required to pe rmit improvements in the design of its products. elmos semiconductor ag data sheet qm-no.: 25ds0093e.0 1 28 / 82
can/lin sbc family with dc/dc voltage regulator e521 .02/03/04/12/13/14 production data ? mar 7, 2016 register wu_src (0x04) msb lsb content lin4 lin3 lin2 lin1 can vdd1 wd wk reset value 0 0 0 0 0 0 0 0 access r r r r r r r r bit description lin4 : 1... wake up from lin4 detected lin3 : 1... wake up from lin3 detected lin2 : 1... wake up from lin2 detected lin1 : 1... wake up from lin1 detected can : 1... wake up from can detected vdd1 : 1... wake up in stop mode due to vdd1 current li mitation exceeded wd : 1... cyclic wake up in stop mode wk : 1... wake up from local wake up pin wk detected table 38: wake up source register. wake up source i s cleared if register is read. elmos semiconductor ag reserves the right to change the detail specifications as may be required to pe rmit improvements in the design of its products. elmos semiconductor ag data sheet qm-no.: 25ds0093e.0 1 29 / 82
can/lin sbc family with dc/dc voltage regulator e521 .02/03/04/12/13/14 production data ? mar 7, 2016 register spi_fail (0x05) msb lsb content lin4 lin3 lin2 lin1 can - wd fsm reset value 0 0 0 0 0 0 0 0 access r r r r r r r r bit description register is cleared by reading via spi lin4 : 1.. lin4 is reason for interrupt, e.g. configuratio n of lin4 in case of not beeing in sbc state normal 0.. lin4 is not reason for interrupt lin3 : 1.. lin3 is reason for interrupt, e.g. configuratio n of lin3 in case of not beeing in sbc state normal 0.. lin3 is not reason for interrupt lin2 : 1.. lin2 is reason for interrupt, e.g. configuratio n of lin2 in case of not beeing in sbc state normal 0.. lin2 is not reason for interrupt lin1 : 1.. lin1 is reason for interrupt, e.g. configuratio n of lin1 in case of not beeing in sbc state normal 0.. lin1 is not reason for interrupt can : 1.. can is reason for interrupt, e.g. configuration of can in case of not beeing in sbc state normal 0.. can is not reason for interrupt wd : 1.. watchdog is reason for interrupt, e.g. configur ation of wd in case of not beeing in sbc state normal 0.. watchdog is not reason for interrupt fsm : 1.. state machine is reason for interrupt, e.g. try ing to change into sbc state sleep with pending wake up 0.. state machine is not reason for interrupt table 39: spi programming failure register. elmos semiconductor ag reserves the right to change the detail specifications as may be required to pe rmit improvements in the design of its products. elmos semiconductor ag data sheet qm-no.: 25ds0093e.0 1 30 / 82
can/lin sbc family with dc/dc voltage regulator e521 .02/03/04/12/13/14 production data ? mar 7, 2016 register vdd_stat (0x1a) msb lsb content vdd2 on vdd2_en pin vdd2oc vdd2 uv - vddcan uv vdd1 uv - reset value 0 0 0 0 0 0 0 0 access r r r r r r r r bit description vdd2 on : 1.. linear voltage regulator vdd2 enabled 0.. linear voltage regulator vdd2 disabled vdd2_en pin : 1.. envdd2 set to logic level 1 0.. envdd2 set to logic level 0 vdd2oc : 1.. vdd2 over current detected 0.. vdd2 over current not detected vdd2 uv : 1.. vdd2 under voltage detected 0.. vdd2 under voltage not detected vddcan uv : 1.. vddcan under voltage detected 0.. vddcan under voltage not detected vdd1 uv : 1.. vdd1 under voltage detected 0.. vdd1 under voltage not detected table 40: vdd1, vdd2 and vddcan status information. elmos semiconductor ag reserves the right to change the detail specifications as may be required to pe rmit improvements in the design of its products. elmos semiconductor ag data sheet qm-no.: 25ds0093e.0 1 31 / 82
can/lin sbc family with dc/dc voltage regulator e521 .02/03/04/12/13/14 production data ? mar 7, 2016 5.2.1 off state the off mode is the unsupplied state. this mode is left automatically if v vs > v s,pu . it is entered automatically if v vs < v s,pd . 5.2.2 init state the sbc is set to state init after v vs,pu is exceeded. the dcdc buck converter vdd1 is switc hed on. the default reset threshold v th4,vdd1,rstn is active. pin rstn is set to l. after reaching reset threshold reset delay time t rstn,vdd1 is applied. then pin rstn is set to h. in case of vdd1 does not start up beyond its reset level state tra nsition to state failsafe is performed after t to,vdd1 . this function helps to prevent higher or even sho rt currents to vdd1 for longer times. transition from sbc state init to sbc state normal must be initiated by spi within t to,init . t to,init starts with rising edge of rstn . the reset output pin rstn is bidirectional and can be overwritten by the ext ernal c. in case of an internal reset extended by an external reset the timeout t wdrstn,to,gnd becomes active at the end of the internal reset du ration. if the timeout is exceeded sbc changes to state failsa fe and fson is set. 5.2.3 normal state state normal is expected to be the main state. all configuration registers are accessable and watchdog is run- ning. watchdog, can, vdd2, wk, fson and lins can be confi gured. low power state stop and very low power state sleep can be entered via spi. if a watchdog trigger failure occurs or rstn is overwritten externally or vdd1 drops below the configurable reset threshold state is changed to failsafe or restart d epending on configuration of bit sbc_cfg.cfg. 5.2.4 stop state lin and can transceivers are off but can be wakeabl e. watchdog cyclic wake up timer can be active. config uration must be performed in state normal in regist ers wd_cfg1 and wd_cfg2 prior entering state stop as de scribed for watchdog configuration change. occurenc e of cyclic wake up generates an interrupt. vdd2 regulator can be active depending on pin envdd2 or bit vdd2_cfg.on. if rstn is overwritten externally the state changed to fai lsafe or restart mode depending on configuration of bit sbc_cfg.cfg. hence the regulator is enabled eve ry t1 n an external reset is detectable only after that ti me only. 5.2.5 vdd1 current observation in sbc state stop a low current consumption is expected in sbc state stop. to save current dcdc is switched off after an initial time t tran,stop . dcdc is enabled periodically for regular recharge phase t on_reg,stop every reload time t1 n . reload time can be configured in register vdd1_cfg. the undervoltage detection remains active. in case of current consumption is too high voltage drops below undervoltage threshold k1 vdd1 and regulator is enabled for t tran,stop . if this happens more than once within t1 n state is changed to sbc state normal and an interrupt is generated. otherwise sbc remains in st ate stop. elmos semiconductor ag reserves the right to change the detail specifications as may be required to pe rmit improvements in the design of its products. elmos semiconductor ag data sheet qm-no.: 25ds0093e.0 1 32 / 82
can/lin sbc family with dc/dc voltage regulator e521 .02/03/04/12/13/14 production data ? mar 7, 2016 system behaviour concerning v vdd1 strongly depends on value of external capacitor. i t is recommended to calculate value of external capacitor with knowledge of overa ll system stop state current consumption and adding a safety margin in order to ensure sbc state stop can be rea ched and kept. accessing register vdd1_cfg is not allowed in sbc s tate failsafe. fig. 3: transition to and from sbc state stop with current observation on vdd1 5.2.6 sleep state lin and can transceivers are off but can be wakeabl e. vdd1 voltage regulator is off and reset signal a t rstn is generated. vdd2 regulator can be active depending on pin envdd2 or bit vdd2_cfg.on. a transition to state sleep with all wake up source s disabled is prohibited. the transistion is ignore d, spi failure bit is set and an interrupt is generated. wake up event causes a transition to state restart. watchdog can be configured to wake up device in sta te sleep. 5.2.7 restart state state restart is an intermediate state being reache d in case of failure conditions or wake up from sta tes sleep or failsafe. state can be left to normal using spi command withi n limited amount of time t to,init . otherwise state failsafe is entered automatically. 5.2.8 failsafe state state failsafe is entered in case of failure condit ion present only. pin fson is activated automatically. vdd1 reg- ulator is switched off. pin rstn is set to low. vdd2 regulator can be active depending on pin envdd2 . elmos semiconductor ag reserves the right to change the detail specifications as may be required to pe rmit improvements in the design of its products. elmos semiconductor ag data sheet qm-no.: 25ds0093e.0 1 33 / 82
can/lin sbc family with dc/dc voltage regulator e521 .02/03/04/12/13/14 production data ? mar 7, 2016 with entering state failsafe all wake up capabiliti es are enabled. in case of a wake up condition stat e restart is entered. in case of an overtemperature failure state restart is entered when overtemperature condition vanishes . 5.2.9 configuration for transition behaviour to mod es failsafe or restart transition behaviour in case of failure either to s bc state failsafe or to sbc state restart can be se tup using external circuitry connected to pin intn . setup of behaviour is performed in state init at th e end of sbc active rstn time t rstn,vdd1 . at this particular point voltage at intn is sensed back. desired behaviour is stored in reg ister sbc_cfg.cfg. for setup purposes during time of determination nei ther internal normal pull up resistor nor internal low side driver are active in intn stage. instead of an internal pull down resistor i s active. there are two possible cases: 1. external pull up present: detect logic level high 2. no external pull up present: detect logic level low diagram fig. 4 shows principal implementation of intn stage. t 1n and t 1p are used for normal operation. for setup phase both t 1n and t 1p are switched off and pull down controlled by t 2n is enabled. recommendation for selection of external pull up re sistance towards vdd1 system with v vdd1 =5v: select value of 85k , e.g. 68k fig. 4: intn internal structure with support for se tup sbc_cfg.cfg implementation of intn stage for normal operation a nd setup of sbc_cfg.cfg. an alternative way to change restart/failsafe behav iour in case of a failure is setting bit sbc_cfg.cf g via spi. but there are some limitations: 1. bit sbc_cfg.cfg can not be set to l via spi if an external pull up exists at pin intn . 2. bit sbc_cfg.cfg can be written in states stop and normal only. 3. bit sbc_cfg.cfg is cleared in states restart and failsafe. elmos semiconductor ag reserves the right to change the detail specifications as may be required to pe rmit improvements in the design of its products. elmos semiconductor ag data sheet qm-no.: 25ds0093e.0 1 34 / 82
can/lin sbc family with dc/dc voltage regulator e521 .02/03/04/12/13/14 production data ? mar 7, 2016 5.2.10 software development function; pin swdm high active pin swdm determines activation of software development func tion. the only way to enable software development function is a high level of pin swdm with internal release of pin rstn in sbc states init or restart. in final application pin swdm must be connected to electrical ground. with software development function enabled followin g changes apply to system behaviour: 1. no watchdog related reset at pin rstn is generated 2. automatic watchdog related transitions to states failsafe or restart are not performed 3. external events at rstn are ignored 4. exceeding of timeout t to,init is ignored all failures are signaled as usual in spi status re gister. all other functional blocks behave as descr ibed. setting pin swdm to low logic level disables software development f unction. 5.2.11 over temperature behaviour ic implements 8 independent temperature sensors: 1. lin1 2. lin2 3. lin3 4. lin4 5. hs-can 6. vdd2 voltage regulator 7. vdd1 dcdc buck converter 8. internal aux. structures in case of over temperature detected in lin or can transceivers corresponding interface is switched of f and an interrupt is set. vdd2 voltage regulator features both warning and ov er temperature shutdown functionality including int errupt gen- eration. vdd1 over temperature detection results in an exter nal reset at rstn . in case of internal auxiliary structures report an over temperature situation system changes to sbc st ate failsafe. if overtemperature vanishes device will e nter sbc state restart. register name address description ot_stat 0x1f over temperature detection status regist er. table 41: registertable elmos semiconductor ag reserves the right to change the detail specifications as may be required to pe rmit improvements in the design of its products. elmos semiconductor ag data sheet qm-no.: 25ds0093e.0 1 35 / 82
can/lin sbc family with dc/dc voltage regulator e521 .02/03/04/12/13/14 production data ? mar 7, 2016 register ot_stat (0x1f) msb lsb content lin4 lin3 lin2 lin1 can vdd2 vdd1 aux reset value 0 0 0 0 0 0 0 0 access r r r r r r r r bit description lin4 : 1.. lin4 over temperature detected 0.. lin4 over temperature not detected lin3 : 1.. lin3 over temperature detected 0.. lin3 over temperature not detected lin2 : 1.. lin2 over temperature detected 0.. lin2 over temperature not detected lin1 : 1.. lin1 over temperature detected 0.. lin1 over temperature not detected can : 1.. can over temperature detected 0.. can over temperature not detected vdd2 : 1.. vdd2 over temperature detected 0.. vdd2 over temperature not detected vdd1 : 1.. vdd1 over temperature detected 0.. vdd1 over temperature not detected aux : 1.. over temperature in other internal aux. structu res detected 0.. over temperature in other internal aux. structu res not detected table 42: over temperature detection status registe r. elmos semiconductor ag reserves the right to change the detail specifications as may be required to pe rmit improvements in the design of its products. elmos semiconductor ag data sheet qm-no.: 25ds0093e.0 1 36 / 82
can/lin sbc family with dc/dc voltage regulator e521 .02/03/04/12/13/14 production data ? mar 7, 2016 5.3 spi communication; pins sck, sdi, sdo, csn the spi interface is used for: ? storing-/and reading can data-/timing and system co nfigurations ? reading diagnosis register by setting csn to low level, the communication can be achieved and by setting to high level leads to d isabling the communication (in this case, pin sdo is high impeda nce). during the transmission data shifts are contr olled by the serial clock signal (sck) according to the followin g rules: ? data is shifted msb first, lsb last ? data is shifted out on the rising edge of sck and i s sampled on the falling edge of sck ? data transmission length is always 16 bit spi write is performed setting msb bit a7 of addres s value to 1. during read bit a7 needs to be 0. fig. 5: spi access bit rw ? 1 : write access ? 0 : read access fig. 6: spi timing diagram spi timing diagram. for configuration of write and read access check corresponding diagrams. elmos semiconductor ag reserves the right to change the detail specifications as may be required to pe rmit improvements in the design of its products. elmos semiconductor ag data sheet qm-no.: 25ds0093e.0 1 37 / 82
can/lin sbc family with dc/dc voltage regulator e521 .02/03/04/12/13/14 production data ? mar 7, 2016 5.4 watchdog; pin rstn design implements watchdog functionality that can b e used in window or timeout mode. watchdog mode dep ends on system state. 5.4.1 time out mode the time out mode is an easier and less secure type of the watchdog modes. a closed window does not ex ist. the watchdog trigger can be applied at any time within the watchdog cycle. a watchdog trigger is detected as a write access to the register wd_trig. the bit trig_bit mu st toggle. a correct watchdog trigger starts a new window period. the period can be configured in registers wd_cfg1 a nd wd_cfg2 in the range from 4ms up to 1024ms using formula 4ms*(1+per[7:0]). in case of an incorrect watchdog trigger the sbc wi ll enter states restart or failsafe depending on co nfigura- tion in sbc_cfg. a watchdog failure generates a res et setting the pin rstn to l for t wd,rstn . the first period always starts with 256ms. the firs t trig_bit must be h. fig. 7: watchdog time out mode fig. 8: watchdog time out mode without trigger 5.4.2 window mode the window mode is the secure type of the watchdog modes. it consists of a closed and an open window. a closed window is 50% of the configured watchdog period. elmos semiconductor ag reserves the right to change the detail specifications as may be required to pe rmit improvements in the design of its products. elmos semiconductor ag data sheet qm-no.: 25ds0093e.0 1 38 / 82
can/lin sbc family with dc/dc voltage regulator e521 .02/03/04/12/13/14 production data ? mar 7, 2016 a triggering of the watchdog is only allowed in the open window. a watchdog trigger is detected as a w rite access to register wd_trig. the bit trig_bit must toggle. a c orrect watchdog trigger starts a new window period. the period can be configured in registers wd_cfg1 a nd wd_cfg2 in the range from 4ms up to 1024ms using formula 4ms*(1+per[7:0]). in case of an incorrect watchdog trigger the sbc wi ll enter sbc state restart or failsafe depending on config- uration in register sbc_cfg. a watchdog generates a reset setting the pin rstn to low for t wd,rstn . the first period always starts with 256ms. the firs t trig_bit must be high. fig. 9: watchdog window mode fig. 10: watchdog window mode no trigger in fow behaviour of watchdog in case of missing trigger in open window. elmos semiconductor ag reserves the right to change the detail specifications as may be required to pe rmit improvements in the design of its products. elmos semiconductor ag data sheet qm-no.: 25ds0093e.0 1 39 / 82
can/lin sbc family with dc/dc voltage regulator e521 .02/03/04/12/13/14 production data ? mar 7, 2016 fig. 11: watchdog window mode trigger in closed win dow behaviour of watchdog in case of trigger in closed window. fig. 12: watchdog window mode no trigger in open wi ndow behaviour of watchdog in case of missing trigger in open window. elmos semiconductor ag reserves the right to change the detail specifications as may be required to pe rmit improvements in the design of its products. elmos semiconductor ag data sheet qm-no.: 25ds0093e.0 1 40 / 82
can/lin sbc family with dc/dc voltage regulator e521 .02/03/04/12/13/14 production data ? mar 7, 2016 fig. 13: safe trigger area 5.4.3 configuration the configuration of watchdog is allowed in sbc sta te normal only. registers wd_cfg1 and wd_cfg2 must be written within one watchdog cycle. the correspon ding bits of wd_cfg1 and wd_cfg2 as well as wd_per1 and wd_per2 must be equal. only in this case the co nfiguration is valid. the configuration currently u sed can be read in registers wd_cfg and wd_per. register name address description wd_cfg 0x08 current watchdog configuration. change of configuration has to be performed using wd_cfg1 and wd_cfg2 including correct watchdo g trigger afterwards within one watchdog cycle in sbc state normal wd_cfg1 0x09 watchdog configuration register 1 wd_cfg2 0x0a watchdog configuration register 2 wd_stat 0x0b watchdog status register wd_per 0x0c current watchdog period. change of period has to be performed using wd_per1 and wd_per2 including correct watchdog trig ger afterwards within one watchdog cycle. wd_trig 0x0d watchdog trigger register wd_per1 0x0e watchdog period register 1 wd_per2 0x0f watchdog period register 2 table 43: watchdog registertable elmos semiconductor ag reserves the right to change the detail specifications as may be required to pe rmit improvements in the design of its products. elmos semiconductor ag data sheet qm-no.: 25ds0093e.0 1 41 / 82
can/lin sbc family with dc/dc voltage regulator e521 .02/03/04/12/13/14 production data ? mar 7, 2016 register wd_cfg (0x08) msb lsb content tbase wd cwk1 cwk0 mode - - - reset value 0 0 0 0 1 0 0 0 access r r r r r r r r bit description tbase : in sbc state normal: 1.. output time base at rxdlin1 on 0.. output time base at rxdlin1 off wd : in sbc state stop, overwrites cwk1: 1.. watchdog on 0.. watchdog off cwk1 : in sbc states stop: 1.. cyclic wake up on 0.. cyclic wake up off cwk0 : in sbc state sleep: 1.. cyclic wake up on 0.. cyclic wake up off mode : 1.. time out mode 0.. window mode table 44: current watchdog configuration. change of configuration has to be performed using wd_cfg1 an d wd_cfg2 including correct watchdog trigger afterwar ds within one watchdog cycle in sbc mode normal register wd_cfg1 (0x09) msb lsb content tbase wd cwk1 cwk0 mode - - - reset value 0 0 0 0 1 0 0 0 access r/w r/w r/w r/w r/w r r r bit description tbase : in sbc state normal: 1.. output time base at rxdlin1 on 0.. output time base at rxdlin1 off wd : in sbc state stop, overwrites cwk1: 1.. watchdog on, 0.. watchdog off cwk1 : in sbc states stop: 1.. cyclic wake up on 0.. cyclic wake up off cwk0 : in sbc state sleep: 1.. cyclic wake up on 0.. cyclic wake up off mode : 1.. time out mode 0.. window mode table 45: watchdog configuration register 1 elmos semiconductor ag reserves the right to change the detail specifications as may be required to pe rmit improvements in the design of its products. elmos semiconductor ag data sheet qm-no.: 25ds0093e.0 1 42 / 82
can/lin sbc family with dc/dc voltage regulator e521 .02/03/04/12/13/14 production data ? mar 7, 2016 register wd_cfg2 (0x0a) msb lsb content - - - mode cwk0 cwk1 wd tbase reset value 0 0 0 1 0 0 0 0 access r r r r/w r/w r/w r/w r/w bit description mode : 1.. time out mode 0.. window mode cwk0 : in sbc state sleep: 1.. cyclic wake up on 0.. cyclic wake up off cwk1 : in sbc states stop: 1.. cyclic wake up on 0.. cyclic wake up off wd : in sbc state stop, overwrites cwk1: 1.. watchdog on 0.. watchdog off tbase : in sbc state normal: 1.. output time base at rxdlin1 on 0.. output time base at rxdlin1 off table 46: watchdog configuration register 2 register wd_stat (0x0b) msb lsb content - - - - - - swdm wdrstn reset value 0 0 0 0 0 0 0 0 access r r r r r r r r bit description swdm : 1.. software development function enabled 0.. software development function disabled wdrstn : 1.. watchdog failure event occurred 0.. no watchdog failure event occured table 47: watchdog status register elmos semiconductor ag reserves the right to change the detail specifications as may be required to pe rmit improvements in the design of its products. elmos semiconductor ag data sheet qm-no.: 25ds0093e.0 1 43 / 82
can/lin sbc family with dc/dc voltage regulator e521 .02/03/04/12/13/14 production data ? mar 7, 2016 register wd_trig (0x0d) msb lsb content - - - - - - - trig reset value 0 0 0 0 0 0 0 0 access r r r r r r r w bit description trig : watchdog trigger, expects alternating content after watchdog enable first bit trig must be 1 table 48: watchdog trigger register register wd_per (0x0c) msb lsb content per[7] per[6] per[5] per[4] per[3] per[2] per[1] pe r[0] reset value 0 0 1 1 1 1 1 1 access r r r r r r r r bit description per[7] : current watchdog period setup per[6] : current watchdog period setup per[5] : current watchdog period setup per[4] : current watchdog period setup per[3] : current watchdog period setup per[2] : current watchdog period setup per[1] : current watchdog period setup per[0] : current watchdog period setup table 49: current watchdog period. change of period has to be performed using wd_per1 and wd_per2 incl ud- ing correct watchdog trigger afterwards within one watchdog cycle. elmos semiconductor ag reserves the right to change the detail specifications as may be required to pe rmit improvements in the design of its products. elmos semiconductor ag data sheet qm-no.: 25ds0093e.0 1 44 / 82
can/lin sbc family with dc/dc voltage regulator e521 .02/03/04/12/13/14 production data ? mar 7, 2016 register wd_per1 (0x0e) msb lsb content per[7] per[6] per[5] per[4] per[3] per[2] per[1] pe r[0] access r/w r/w r/w r/w r/w r/w r/w r/w bit description per[7] : watchdog period setup per[6] : watchdog period setup per[5] : watchdog period setup per[4] : watchdog period setup per[3] : watchdog period setup per[2] : watchdog period setup per[1] : watchdog period setup per[0] : watchdog period setup table 50: watchdog period register 1 register wd_per2 (0x0f) msb lsb content per[0] per[1] per[2] per[3] per[4] per[5] per[6] pe r[7] access r/w r/w r/w r/w r/w r/w r/w r/w bit description per[0] : watchdog period setup per[1] : watchdog period setup per[2] : watchdog period setup per[3] : watchdog period setup per[4] : watchdog period setup per[5] : watchdog period setup per[6] : watchdog period setup per[7] : watchdog period setup table 51: watchdog period register 2. elmos semiconductor ag reserves the right to change the detail specifications as may be required to pe rmit improvements in the design of its products. elmos semiconductor ag data sheet qm-no.: 25ds0093e.0 1 45 / 82
can/lin sbc family with dc/dc voltage regulator e521 .02/03/04/12/13/14 production data ? mar 7, 2016 5.4.4 watchdog timing adjustment for very exact watchdog trigger requirements an int ernal time base with target frequency of 7.8125 khz can be con- nected to pin rxdlin1 . this function can be enabled accessing register wd_ cfg.tbase with correct access valid for watchdog co nfigura- tion. function needs to disabled via spi again in o rder to receive messages using lin1 again. period minimum period maximum period 4096 us * (wd_per + 1) (period - 256 us) /1.1 (period + 256 us) /0.88 table 52: watchdog period and accuracy elmos semiconductor ag reserves the right to change the detail specifications as may be required to pe rmit improvements in the design of its products. elmos semiconductor ag data sheet qm-no.: 25ds0093e.0 1 46 / 82
can/lin sbc family with dc/dc voltage regulator e521 .02/03/04/12/13/14 production data ? mar 7, 2016 5.4.5 external reset / reset clamping if rstn is overwritten externally seven cases have to be distinguished. please also check figure fig. 14 for details. 1. the sbc wants to give a reset and an external sou rce pulls the rstn line down. after the time the sb c want to release the rstn a timeout t wdrstn,to,gnd starts. if no timeout occurs (first section in fig ure fig. 14) sbc state and fson remain unchanged. 2. if the timeout occurs and the sbc detects a rstn clamp to gnd the sbc switches to either state fails afe or to state restart depending on configuration of bit sbc_cfg.cfg and the fson pin is set (second section in figure fig. 14). 3. the sbc wants to give a reset and an external sou rce pulls the rstn line up dominantly. at the time sbc usu- ally releases the reset a clamp to vdd1 is detected . so sbc holds down the reset and starts timeout t wdrstn,to,vdd1 . if the dominant pull up releases while the timeou t runs the sbc gives a regular reset and fson remains unchanged (third section in figure fig. 14) . 4. if the dominant pull up does not release while th e timeout runs sbc switches to either state failsaf e or to state restart depending on configuration of bit sbc _cfg.cfg and fson is set (fourth section in figure fig. 14). 5. the sbc does not want to give a reset and an exte rnal source pulls down pin rstn . there are two configura- tions. configuration one is sbc_cfg.clamp is set to one. this causes timeout t wdrstn,to,gnd starting. if no timeout occurs ( fifth section in figure fig. 14) the state is changed to restart and fson is unchanged. 6. if the timeout occurs and the sbc detects a rstn clamp to gnd the sbc switches either to mode failsa fe or to mode restart depending on configuration of bi t sbc_cfg.cfg and pin fson is set (sixth section in figure fig. 14). 7. configuration two is sbc_cfg.clamp is set to zero . no timeout starts and the sbc detects a rstn clam p to gnd as soon as an external clamp to gnd occurs. in case of this the sbc switches to either mode failsa fe or to mode restart depending on configuration of bi t sbc_cfg.cfg and pin fson is set (seventh section in figure fig. 14). fig. 14: different rstn behaviour behaviour of rstn and configuration options 5.5 local wake up; pin wk the device can be woken up from states sleep and fa ilsafe via pin wk with either a rising or a falling edge. the edge sensitivity can be configured in register wk_cfg. to suppress glitches the input pin is debou nced with twk,deb. the wake up event is signaled at pin intn if it is configured in register wk_cfg. if the local wake up is not used in application, th e pin wk has to be connected to pin vs. a transition into state sleep is prohibited with a pending wake up request. the request must be cleare d via spi reading register wu_src. register name address description wk_cfg 0x10 configuration register of pin wk. register is writeable in sbc state normal only. in sbc states init, restart or failsafe all b its are set to h. table 53: wk registertable elmos semiconductor ag reserves the right to change the detail specifications as may be required to pe rmit improvements in the design of its products. elmos semiconductor ag data sheet qm-no.: 25ds0093e.0 1 47 / 82
can/lin sbc family with dc/dc voltage regulator e521 .02/03/04/12/13/14 production data ? mar 7, 2016 register wk_cfg (0x10) msb lsb content - - - - - - fall rise reset value 0 0 0 0 0 0 1 1 access r r r r r r r/w r/w bit description fall : a falling edge at pin wk leads to a wake up event. 1) rise : a rising edge at pin wk leads to a wake up event. 1) table 54: configuration register of pin wk 1) in sbc states init, restart or failsafe all bits are set to h. elmos semiconductor ag reserves the right to change the detail specifications as may be required to pe rmit improvements in the design of its products. elmos semiconductor ag data sheet qm-no.: 25ds0093e.0 1 48 / 82
can/lin sbc family with dc/dc voltage regulator e521 .02/03/04/12/13/14 production data ? mar 7, 2016 5.6 lin transceiver; pins lin1 to lin4, txdlin1 to txdlin4, rxdlin1 to rxdlin4, gnd- lin 5.6.1 characteristics the lin bus physical interface is implemented as a lin 2.1 standard high-voltage single wire interface (iso 9141) for baud rates from 2.4kbds to 20.4kbds. the lin bu s has two logical values; the dominant state (bus v oltage near gnd) represents logical low level and the recessive state (bus voltage near vs) represents logical hig h level. in the recessive state the bus is pulled high by an in ternal pull-up resistor (typ. 30 k ) and a diode in series, so no external pull-up components are required for slave applications. master applications require an additi onal external pull-up resistor and a series diode. the lin protoc ol output data stream on the txd signal is converte d into the lin bus signal through a current limited, wave-shaping low-side driver with control as outlined by the lin physical layer specification revision 2.1. the receiver converts t he data stream from the bus and outputs it to rxd. fig. 15: lin transceiver physical layer timing the lin transceiver can handle a bus voltage swing from +40v down to ground and survives -27v. the dev ice also prevents back feed current through the lin pin to t he supply pin in case of a ground shift / loss or s upply voltage disconnection. in sleep mode the lin block requires a very low qui escent current by using a special wake up comparato r allowing the remote wakeup via the lin bus. the sleep mode c an be activated during recessive or dominant level of lin bus line. elmos semiconductor ag reserves the right to change the detail specifications as may be required to pe rmit improvements in the design of its products. elmos semiconductor ag data sheet qm-no.: 25ds0093e.0 1 49 / 82
can/lin sbc family with dc/dc voltage regulator e521 .02/03/04/12/13/14 production data ? mar 7, 2016 5.6.2 lin flash mode a flash mode allows an increasing of the transmit b aud rate up to 115kbds and the receiver baud rate u p to 250kbds. the feature is configured in register linx _cfg. 5.6.3 lin wake up the device can be woken up remotely using correspon ding pin linx . the wake up capability can be switched on in corresponding register linx_cfg. in state failsafe this feature is enabled regardless of configuration . when a wake up is recognized, the corresponding fla g in register wu_src is set. the device supports two different behaviours. 1. a falling edge at pin lin followed by a dominant bus level v lin,dom maintained for a time period t lin,wu results in a remote wake up request. 2. a falling edge at pin lin followed by a dominant bus level v lin,dom maintained for a time period t lin,wu , followed by a rising edge results in a remote wake up request. fig. 16: lin wake up in mode sleep elmos semiconductor ag reserves the right to change the detail specifications as may be required to pe rmit improvements in the design of its products. elmos semiconductor ag data sheet qm-no.: 25ds0093e.0 1 50 / 82
can/lin sbc family with dc/dc voltage regulator e521 .02/03/04/12/13/14 production data ? mar 7, 2016 fig. 17: lin wake up in mode init fig. 18: lin wake up at rising edge in mode sleep elmos semiconductor ag reserves the right to change the detail specifications as may be required to pe rmit improvements in the design of its products. elmos semiconductor ag data sheet qm-no.: 25ds0093e.0 1 51 / 82
can/lin sbc family with dc/dc voltage regulator e521 .02/03/04/12/13/14 production data ? mar 7, 2016 fig. 19: lin wake up at rising edge in mode init 5.6.4 lin failure detection and recovery all local or bus failures are signaled in register linx_stat. there are two possibilities to recover the normal o peration after a failure: ? sending two spi commands for lin normal mode, first disable receiver, second enable receiver ? if rxd is dominant while txd is recessive since lin receives dominant bus levels again without driving the bus dominant by itself txd dominant clamping failure this failure can only be detected if the linx trans mitter is enabled, e.g. if bit tr in register linx_ cfg is set to high. if txdx is clamped dominant for longer than t lin,txd,dom the transmitter is disabled and a failure flag is set. rxd dominant clamping failure this failure can be detected if the receiver is ena bled, e.g. if bit tr in register linx_cfg is set. i f rxdx is clamped to dominant level for 4 consecutive linx cycles the transmitter is disabled and a failure flag is set. rxd recessive clamping failure this failure can be detected if the receiver is ena bled, e.g. bit tr in register linx_cfg is set. if rxdx is clamped to recessive level for 4 consecutive linx cycles the transmitter is disabled and a failure f lag is set. bus dominant clamping failure this failure can be detected if the receiver is ena bled, e.g. if bit tr in register linx_cfg is set. i f linx is clamped to low for longer than t lin,bus,dom a failure flag is set. the transmitter is not disa bled. elmos semiconductor ag reserves the right to change the detail specifications as may be required to pe rmit improvements in the design of its products. elmos semiconductor ag data sheet qm-no.: 25ds0093e.0 1 52 / 82
can/lin sbc family with dc/dc voltage regulator e521 .02/03/04/12/13/14 production data ? mar 7, 2016 ot failure if ot occurs transmitter is disabled and a failure flag is set. the transmitter is enabled if the temp erature falls below its threshold and if the conditions for the failure recovery are present. txd to rxd clamping failure this failure can only be detected if the transmitte r is enabled. pin txdlinx is set to low that linx becomes domin- ant. afterwards pin rxdlinx is set to low too controlled by the receiver. in c ase of error c52ondition present pin txdlinx can not be released to high because the driver of rxdlinx is much stronger. if txdlinx is clamped dominant for longer than t lin,txd,dom the transmitter is disabled and a failure flag is set. 5.6.5 lin configuration all configuration registers are writeable in state normal only . register name address description lin_cfg 0x06 shortcut to lin1-4 tr and rc configurati on bits lin1_cfg 0x20 configuration register for lin1 lin_int 0x21 lin interrupt register lin1_stat 0x22 status register for lin1 lin2_cfg 0x24 configuration register for lin2 lin2_stat 0x26 status register for lin2 lin3_cfg 0x28 configuration register for lin3 lin3_stat 0x2a status register for lin3 lin4_cfg 0x2c configuration register for lin4 lin4_stat 0x2e status register for lin4 table 55: lin registertable register lin_int (0x21) msb lsb content lin4 lin3 lin2 lin1 - - - - reset value 0 0 0 0 0 0 0 0 access r r r r r r r r bit description lin4 : 1.. lin4 is reason for interrupt 0.. lin4 is not reason for interrupt lin3 : 1.. lin3 is reason for interrupt 0.. lin3 is not reason for interrupt lin2 : 1.. lin2 is reason for interrupt 0.. lin2 is not reason for interrupt lin1 : 1.. lin1 is reason for interrupt 0.. lin1 is not reason for interrupt table 56: lin interrupt register elmos semiconductor ag reserves the right to change the detail specifications as may be required to pe rmit improvements in the design of its products. elmos semiconductor ag data sheet qm-no.: 25ds0093e.0 1 53 / 82
can/lin sbc family with dc/dc voltage regulator e521 .02/03/04/12/13/14 production data ? mar 7, 2016 register lin1_cfg (0x20) msb lsb content - failint flash wuint wucfg wu tr rc reset value 0 0 0 0 1 1 0 0 access r r/w r/w r/w r/w r/w r/w r/w bit description failint : 1...interrupt enabled for lin failures, could only be set if rc is set. this is locked by hardware. 0...interrupt disabled for lin failures flash : the flash mode deactivates filtering and provide s a baud rate of up to 125kbaud for transmitting and 250kbaud for receiving. 1...flash mode enabled 0...flash mode disabled wuint : 1...interrupt enabled if wu is detected 0...interrupt disabled if wu is detected wucfg : 1... wake up is performed with next rising edge aft er lin wake up debounce time 0.. wake up is performed after lin wake up debounce time wu : 1...wake up capability enabled, could only be set i f rc and tr are not set. this is locked by hardware. 0...wake up capability disabled tr : 1...transmitter enabled, rc is enabled automaticall y, wu is cleared 0...transmitter disabled rc : 1...receiver enabled, read bus only, wu is cleared 0...receiver disabled table 57: configuration register for lin1 elmos semiconductor ag reserves the right to change the detail specifications as may be required to pe rmit improvements in the design of its products. elmos semiconductor ag data sheet qm-no.: 25ds0093e.0 1 54 / 82
can/lin sbc family with dc/dc voltage regulator e521 .02/03/04/12/13/14 production data ? mar 7, 2016 register lin1_stat (0x22) msb lsb content - bus short txddom busdom rxdrec rxddom - - reset value 0 0 0 0 0 0 0 0 access r r r r r r r r bit description bus short : 1...lin short circuit detected 0...lin short circuit not detected txddom : 1...txd permanent dominant clamping timeout exceede d 0...txd permanent dominant clamping timeout not exc eeded busdom : 1...lin permanent dominant clamping timeout exceede d 0...lin permanent dominant clamping timeout not exc eeded rxdrec : 1...rxd permanent recessive clamping timeout exceed ed 0...rxd permanent recessive clamping timeout not ex ceeded rxddom : 1...rxd permanent dominant clamping timeout exceede d 0...rxd permanent dominant clamping timeout not exc eeded table 58: status register for lin1 elmos semiconductor ag reserves the right to change the detail specifications as may be required to pe rmit improvements in the design of its products. elmos semiconductor ag data sheet qm-no.: 25ds0093e.0 1 55 / 82
can/lin sbc family with dc/dc voltage regulator e521 .02/03/04/12/13/14 production data ? mar 7, 2016 register lin2_cfg (0x24) msb lsb content - failint flash wuint wucfg wu tr rc reset value 0 0 0 0 1 1 0 0 access r r/w r/w r/w r/w r/w r/w r/w bit description failint : 1...interrupt enabled for lin failures, could only be set if rc is set. this is locked by hardware. 0...interrupt disabled for lin failures flash : the flash mode deactivates filtering and provide s a baud rate of up to 125kbaud for transmitting and 250kbaud for receiving. 1...flash mode enabled 0...flash mode disabled wuint : 1...interrupt enabled if wu is detected 0...interrupt disabled if wu is detected wucfg : 1... wake up is performed with next rising edge aft er lin wake up debounce time 0.. wake up is performed after lin wake up debounce time wu : 1...wake up capability enabled, could only be set i f rc and tr are not set. this is locked by hardware. 0...wake up capability disabled tr : 1...transmitter enabled, rc is enabled automaticall y, wu is cleared 0...transmitter disabled rc : 1...receiver enabled, read bus only, wu is cleared 0...receiver disabled table 59: configuration register for lin2 elmos semiconductor ag reserves the right to change the detail specifications as may be required to pe rmit improvements in the design of its products. elmos semiconductor ag data sheet qm-no.: 25ds0093e.0 1 56 / 82
can/lin sbc family with dc/dc voltage regulator e521 .02/03/04/12/13/14 production data ? mar 7, 2016 register lin2_stat (0x26) msb lsb content - bus short txddom busdom rxdrec rxddom - - reset value 0 0 0 0 0 0 0 0 access r r r r r r r r bit description bus short : 1...lin short circuit detected 0...lin short circuit not detected txddom : 1...txd permanent dominant clamping timeout exceede d 0...txd permanent dominant clamping timeout not exc eeded busdom : 1...lin permanent dominant clamping timeout exceede d 0...lin permanent dominant clamping timeout not exc eeded rxdrec : 1...rxd permanent recessive clamping timeout exceed ed 0...rxd permanent recessive clamping timeout not ex ceeded rxddom : 1...rxd permanent dominant clamping timeout exceede d 0...rxd permanent dominant clamping timeout not exc eeded table 60: status register for lin2 elmos semiconductor ag reserves the right to change the detail specifications as may be required to pe rmit improvements in the design of its products. elmos semiconductor ag data sheet qm-no.: 25ds0093e.0 1 57 / 82
can/lin sbc family with dc/dc voltage regulator e521 .02/03/04/12/13/14 production data ? mar 7, 2016 register lin3_cfg (0x28) - should not be used with e521.02 and e521. 12 msb lsb content - failint flash wuint wucfg wu tr rc reset value 0 0 0 0 1 1 0 0 access r r/w r/w r/w r/w r/w r/w r/w bit description failint : 1...interrupt enabled for lin failures, could only be set if rc is set. this is locked by hardware. 0...interrupt disabled for lin failures flash : the flash mode deactivates filtering and provide s a baud rate of up to 125kbaud for transmitting and 250kbaud for receiving. 1...flash mode enabled 0...flash mode disabled wuint : 1...interrupt enabled if wu is detected 0...interrupt disabled if wu is detected wucfg : 1... wake up is performed with next rising edge aft er lin wake up debounce time 0.. wake up is performed after lin wake up debounce time wu : 1...wake up capability enabled, could only be set i f rc and tr are not set. this is locked by hardware. 0...wake up capability disabled tr : 1...transmitter enabled, rc is enabled automaticall y, wu is cleared 0...transmitter disabled rc : 1...receiver enabled, read bus only, wu is cleared 0...receiver disabled table 61: configuration register for lin3 elmos semiconductor ag reserves the right to change the detail specifications as may be required to pe rmit improvements in the design of its products. elmos semiconductor ag data sheet qm-no.: 25ds0093e.0 1 58 / 82
can/lin sbc family with dc/dc voltage regulator e521 .02/03/04/12/13/14 production data ? mar 7, 2016 register lin3_stat (0x2a) - should not be used with e521.02 and e521. 12 msb lsb content - bus short txddom busdom rxdrec rxddom - - reset value 0 0 0 0 0 0 0 0 access r r r r r r r r bit description bus short : 1...lin short circuit detected 0...lin short circuit not detected txddom : 1...txd permanent dominant clamping timeout exceede d 0...txd permanent dominant clamping timeout not exc eeded busdom : 1...lin permanent dominant clamping timeout exceede d 0...lin permanent dominant clamping timeout not exc eeded rxdrec : 1...rxd permanent recessive clamping timeout exceed ed 0...rxd permanent recessive clamping timeout not ex ceeded rxddom : 1...rxd permanent dominant clamping timeout exceede d 0...rxd permanent dominant clamping timeout not exc eeded table 62: status register for lin3 elmos semiconductor ag reserves the right to change the detail specifications as may be required to pe rmit improvements in the design of its products. elmos semiconductor ag data sheet qm-no.: 25ds0093e.0 1 59 / 82
can/lin sbc family with dc/dc voltage regulator e521 .02/03/04/12/13/14 production data ? mar 7, 2016 register lin4_cfg (0x2c) - should not be used with e521.02, e521.03, e521.12 and e521.13 msb lsb content - failint flash wuint wucfg wu tr rc reset value 0 0 0 0 1 1 0 0 access r r/w r/w r/w r/w r/w r/w r/w bit description failint : 1...interrupt enabled for lin failures, could only be set if rc is set. this is locked by hardware. 0...interrupt disabled for lin failures flash : the flash mode deactivates filtering and provide s a baud rate of up to 125kbaud for transmitting and 250kbaud for receiving. 1...flash mode enabled 0...flash mode disabled wuint : 1...interrupt enabled if wu is detected 0...interrupt disabled if wu is detected wucfg : 1... wake up is performed with next rising edge aft er lin wake up debounce time 0.. wake up is performed after lin wake up debounce time wu : 1...wake up capability enabled, could only be set i f rc and tr are not set. this is locked by hardware. 0...wake up capability disabled tr : 1...transmitter enabled, rc is enabled automaticall y, wu is cleared 0...transmitter disabled rc : 1...receiver enabled, read bus only, wu is cleared 0...receiver disabled table 63: configuration register for lin4 elmos semiconductor ag reserves the right to change the detail specifications as may be required to pe rmit improvements in the design of its products. elmos semiconductor ag data sheet qm-no.: 25ds0093e.0 1 60 / 82
can/lin sbc family with dc/dc voltage regulator e521 .02/03/04/12/13/14 production data ? mar 7, 2016 register lin4_stat (0x2e) - should not be used with e521.02, e521.03, e521.12 and e521.13 msb lsb content - bus short txddom busdom rxdrec rxddom - - reset value 0 0 0 0 0 0 0 0 access r r r r r r r r bit description bus short : 1...lin short circuit detected 0...lin short circuit not detected txddom : 1...txd permanent dominant clamping timeout exceede d 0...txd permanent dominant clamping timeout not exc eeded busdom : 1...lin permanent dominant clamping timeout exceede d 0...lin permanent dominant clamping timeout not exc eeded rxdrec : 1...rxd permanent recessive clamping timeout exceed ed 0...rxd permanent recessive clamping timeout not ex ceeded rxddom : 1...rxd permanent dominant clamping timeout exceede d 0...rxd permanent dominant clamping timeout not exc eeded table 64: status register for lin4 register lin_cfg (0x06) msb lsb content tr4 rc4 tr3 rc3 tr2 rc2 tr1 rc1 reset value 0 0 0 0 0 0 0 0 access r/w r/w r/w r/w r/w r/w r/w r/w bit description tr4 : same as lin4_cfg.tr. should set to 0 with e521.0 2, e521.03, e521.12 and e521.13 rc4 : same as lin4_cfg.rc. should set to 0 with e521.0 2, e521.03, e521.12 and e521.13 tr3 : same as lin3_cfg.tr. should set to 0 with e521.0 2 and e521.12 rc3 : same as lin3_cfg.rc. should set to 0 with e521.0 2 and e521.12 tr2 : same as lin2_cfg.tr rc2 : same as lin2_cfg.rc tr1 : same as lin1_cfg.tr rc1 : same as lin1_cfg.rc table 65: shortcut to lin1-4 tr and rc configuratio n bits elmos semiconductor ag reserves the right to change the detail specifications as may be required to pe rmit improvements in the design of its products. elmos semiconductor ag data sheet qm-no.: 25ds0093e.0 1 61 / 82
can/lin sbc family with dc/dc voltage regulator e521 .02/03/04/12/13/14 production data ? mar 7, 2016 5.7 hs-can transceiver; pins canh, canl, rxdcan, tx dcan, vddcan the hs-can transceiver is compatible to iso 11898-5 . canh and canl interface the can protocol controller to hs-can physical layer wires. data rate can be s elected up to 1megbaud. fig. 20: hs-can bus timing 5.7.1 can wake up the device is capable detecting wake up pattern at the can bus if configured. a wake up pattern ideall y consists of four consecutive symbols dominant, recessive, domin ant and recessive. the dominant bus states have to be longer than t can,wake_bus_dom and the recessive bus states have to be longer tha n t can,wake_bus_rec . the pattern must be applied within t wake2 . when the wake up pattern is recognized, the corresp onding flag in register wu_src is set.pin intn is set low if bit can_cfg.wuint was set high. pin rxdcan is set to low until bit can_cfg.rc is set high or r egister wu_src is read. fig. 21: remote wakeup pattern elmos semiconductor ag reserves the right to change the detail specifications as may be required to pe rmit improvements in the design of its products. elmos semiconductor ag data sheet qm-no.: 25ds0093e.0 1 62 / 82
can/lin sbc family with dc/dc voltage regulator e521 .02/03/04/12/13/14 production data ? mar 7, 2016 5.7.2 can failure detection and recovery all can related local or bus failures are signaled in register can_stat. there are two possibilities to recover the normal o peration after a failure: ? sending the spi command for can normal operation mo de ? if rxd is dominant while txd is recessive txd dominant clamping failure this failure can only be detected if the transmitte r is enabled, e.g. bit tr in register can_cfg is se t to high. if txd- can is clamped dominant for longer than t can,txd,dom the transmitter is disabled and a failure flag is set. rxd dominant clamping failure this failure can be detected if the receiver is ena bled, e.g. bit rc or tr in register can_cfg is set. if rxdcan is clamped low for 4 consecutive can cycles the transmitter is disabled and a failure f lag is set. rxd recessive clamping failure this failure can be detected if the receiver is ena bled, e.g. bit rc or tr in register can_cfg is set. if rxdcan is clamped recessive level for 4 consecutive can cycles the transmitter is disabled and a failure f lag is set. bus dominant clamping failure this failure can be detected if the receiver is ena bled, e.g. bit rc or tr in register can_cfg is set. if can is clamped dominant for longer than t can,bus,dom a failure flag is set. the transmitter is not disa bled. txd to rxd clamping failure this failure can only be detected if the transmitte r is enabled. pin txdcan is set to low that can becomes domin- ant. afterwards pin rxdcan is set to low too controlled by the receiver. in c ase of error condition present pin txd- can can not be released to high because the driver of rxdcan is much stronger. if txdcan is clamped domin- ant for longer than t can,txd,dom the transmitter is disabled and a failure flag is set. ot failure if ot occurs the transmitter is disabled and a fail ure flag is set. the transmitter is enabled again i f the temperature falls below its threshold and the conditions for th e failure recovery are present. canh to gnd clamping failure this failure can be detected if the transmitter is enabled, e.g. bit tr in register can_cfg is set. if the short is present for 4 consecutive can cycles of at least t bus,fail a failure flag is set. the transmitter is not disab led. the fail- ure is cleared if canh is not clamped to gnd anymor e. elmos semiconductor ag reserves the right to change the detail specifications as may be required to pe rmit improvements in the design of its products. elmos semiconductor ag data sheet qm-no.: 25ds0093e.0 1 63 / 82
can/lin sbc family with dc/dc voltage regulator e521 .02/03/04/12/13/14 production data ? mar 7, 2016 canl to gnd clamping failure this failure can be detected if the transmitter is enabled, e.g. bit tr in register can_cfg is set. if the short is present for 4 consecutive can cycles of at least t bus,fail a failure flag is set. the transmitter is not disab led. the fail- ure is cleared if canh is not clamped to gnd anymor e. canh to vddcan/vs clamping failure this failure can be detected if the transmitter is enabled, e.g. bit tr in register can_cfg is set. if the short is present for 4 consecutive can cycles of at least t bus,fail a failure flag is set. the transmitter is not disab led. the fail- ure is cleared if canh is not clamped to vddcan/vs anymore. canl to vcc/vs clamping failure this failure can be detected if the transmitter is enabled, e.g. bit rc or tr in register can_cfg is s et. if the short is present for 4 consecutive can cycles of at least t bus,fail a failure flag is set. the transmitter is not disab led. the failure is cleared if canh is not clamped to vddcan/vs anymore. 5.7.3 can configuration register name address description can_cfg 0x30 configuration register for can can_stat 0x32 status register for can table 66: can registertable register can_cfg (0x30) msb lsb content - failint - wuint bf wu tr rc reset value 0 0 0 1 0 1 0 0 access r r/w r r/w r/w r/w r/w r/w bit description failinten : 1...interrupt enabled for can failures 0...interrupt disabled for can failures wuint : 1...interrupt enabled if wu is detected 0...interrupt disabled if wu is detected bf : 1.. can bus short failure detection enabled 0.. can bus short failure detection disabled wu : 1...wake up capability enabled, only valid if rc and tr are 0 0...wake up capability disabled tr : 1...transmitter enabled, rc is enabled automatic ally, wu is masked 0...transmitter disabled rc : 1...receiver enabled, listen only, wu is masked 0...receiver disabled table 67: configuration register for can elmos semiconductor ag reserves the right to change the detail specifications as may be required to pe rmit improvements in the design of its products. elmos semiconductor ag data sheet qm-no.: 25ds0093e.0 1 64 / 82
can/lin sbc family with dc/dc voltage regulator e521 .02/03/04/12/13/14 production data ? mar 7, 2016 register can_stat (0x32) msb lsb content chvcc chgnd clvcc clgnd rxdrec rxddom busdom txdd om reset value 0 0 0 0 0 0 0 0 access r r r r r r r r bit description chvcc : 1.. canh to vcc or vs clamping detected 0.. canh to vcc or vs clamping not detected chgnd : 1.. canh to gnd clamping detected 0.. canh to gnd clamping not detected clvcc : 1.. canl to vcc or vs clamping detected 0.. canl to vcc or vs clamping not detected clgnd : 1.. canl to gnd clamping detected 0.. canl to gnd clamping not detected rxdrec : 1.. rxd permanent recessive clamping timeout exce eded 0.. rxd permanent recessive clamping timeout not ex ceeded rxddom : 1.. rxd permanent dominant clamping timeout excee ded 0.. rxd permanent dominant clamping timeout not exc eeded busdom : 1.. can permanent dominant clamping timeout excee ded 0.. can permanent dominant clamping timeout not exc eeded txddom : 1.. txd permanent dominant clamping timeout excee ded 0.. txd permanent dominant clamping timeout not exc eeded table 68: status register for can elmos semiconductor ag reserves the right to change the detail specifications as may be required to pe rmit improvements in the design of its products. elmos semiconductor ag data sheet qm-no.: 25ds0093e.0 1 65 / 82
can/lin sbc family with dc/dc voltage regulator e521 .02/03/04/12/13/14 production data ? mar 7, 2016 5.8 limp home support; pin fson sbc features limp home support using pin fson . activation of fson is not linked to sbc mode failsafe only. please ch eck sections 5.8.1 and 5.2 for details. in order to activate output pin fson using spi command. both registers fson_cfg1 and fs on_cfg2 need to be accessed within one watchdog period for system s afety reasons. if contents of registers is equal pi n fson is activated when watchdog is triggered. otherwise no change is made. register name address description fson_stat 0x02 fson status register. fson_cfg1 0x1b fson configuration register 1 fson_cfg2 0x1c fson configuration register 2 table 69: fson registertable register fson_cfg1 (0x1b) msb lsb content clamp - - spi - - - - reset value 1 0 0 0 0 0 0 0 access r/w r r r/w r r r r bit description clamp : 1.. external reset shorter than t wdrstn,to,gnd will not lead to fson set 0.. external reset leads to fson set immediately spi : 1.. activate fson 0.. deactivate fson table 70: fson configuration register 1 register fson_cfg2 (0x1c) msb lsb content - - - - spi - - clamp reset value 0 0 0 0 0 0 0 1 access r r r r r/w r r r/w bit description spi : 1.. activate fson 0.. deactivate fson clamp : 1.. external reset shorter than t wdrstn,to,gnd will not lead to fson set 0.. external reset leads to fson set immediately table 71: fson configuration register 2 elmos semiconductor ag reserves the right to change the detail specifications as may be required to pe rmit improvements in the design of its products. elmos semiconductor ag data sheet qm-no.: 25ds0093e.0 1 66 / 82
can/lin sbc family with dc/dc voltage regulator e521 .02/03/04/12/13/14 production data ? mar 7, 2016 register fson_stat (0x02) msb lsb content - vdd1uv wd ot initto rstnsc fson_spi fson_int reset value 0 0 0 0 0 0 0 0 access r r r r r r r r bit description vdd1uv : 1.. vdd1 under voltage detected 0.. vdd1 under voltage not detected wd : 1..watchdog trigger failure detected 0..watchdog trigger failure not detected ot : 1..over temperature detected 0..over temperature not detected initto : 1..timeout in mode init detected 0..timeout in mode init not detected rstnsc : 1.. rstn clamped low externally 0.. rstn not clamped low externally fson_spi : 1.. fson activated via spi 0.. fson not activated via spi fson_int : 1.. fson activated due to failsafe condition detected 0.. fson not activated due to no failsafe condition detecte d table 72: fson status register. elmos semiconductor ag reserves the right to change the detail specifications as may be required to pe rmit improvements in the design of its products. elmos semiconductor ag data sheet qm-no.: 25ds0093e.0 1 67 / 82
can/lin sbc family with dc/dc voltage regulator e521 .02/03/04/12/13/14 production data ? mar 7, 2016 5.8.1 activation of fson fson is activated in following cases: 1. sbc init mode not left within time t to,init 2. vdd1 time out t to,vdd1 3. activated by spi command accessing fson_cfg1.fson _spi and fson_cfg2.fson_spi within one watch- dog cycle 4. permanent clamping of rstn to gnd 5. permanent clamping of rstn to vdd1 6. external reset on rstn (partly configurable withs bc_cfg.clamp) 7. over temperature 8. watchdog failure fig. 22: activation of fson activation sources for limp home output fson 5.8.2 deactivation of fson fson is deactivated in following cases: 1. c sent deactivation command via spi and sbc is in s tate normal and c sent correct watchdog trigger 2. vs falls below vs vs,pd elmos semiconductor ag reserves the right to change the detail specifications as may be required to pe rmit improvements in the design of its products. elmos semiconductor ag data sheet qm-no.: 25ds0093e.0 1 68 / 82
can/lin sbc family with dc/dc voltage regulator e521 .02/03/04/12/13/14 production data ? mar 7, 2016 fig. 23: deactivation of fson deactivation sources for limp home output fson 5.9 interrupt; pin intn the interrupt pin is driven low if the following in terrupt sources/conditions occur: ? wake up event at can, lin or wk, cyclic wake up ? over temperature warning ? over temperature shut down ? under voltage at vdd1 or vdd2 ? communication failures at can or lin interrupts can be enabled in configuration register s of the corresponding modules. for over temperature and under voltage the appearan ce and disappearance is signaled via an interrupt. therefore after spi reading of interrupt source pin intn is not blocked if the interrupt condition is still active. in order to evaluate detailed reason for interrupt read corresponding status registers. register name address description int 0x03 interrupt status register vdd_stat 0x1a vdd1, vdd2 and vddcan status informatio n. table 73: intn registertable elmos semiconductor ag reserves the right to change the detail specifications as may be required to pe rmit improvements in the design of its products. elmos semiconductor ag data sheet qm-no.: 25ds0093e.0 1 69 / 82
can/lin sbc family with dc/dc voltage regulator e521 .02/03/04/12/13/14 production data ? mar 7, 2016 register int (0x03) msb lsb content can lin wake vddx otwarn ot fsm/spi - reset value 0 0 0 0 0 0 0 0 access r r r r r r r r bit description can : 1... hs-can interface is reason for interrupt lin : 1... at least one of the lin interfaces is reaso n for interrupt wake : 1... wake up event is reason for interrupt vddx : 1... under voltage condition is reason for inter rupt otwarn : 1... over temperature warning level crossing is reason for interrupt ot : 1... over temperature shutdown level crossing is reason for interrupt fsm/spi : 1... fsm or spi are reasons for interrupt table 74: interrupt status register register vdd_stat (0x1a) msb lsb content vdd2 on vdd2 ena pad vdd2oc vdd2 uv - vddcan uv vdd1 uv - reset value 0 0 0 0 0 0 0 0 access r r r r r r r r bit description vdd2 on : 1..linear voltage regulator vdd2 enabled 0..linear voltage regulator vdd2 disabled vdd2 ena pad : 1.. envdd2 set to logic level 1 0.. envdd2 set to logic level 0 vdd2oc : 1.. vdd2 over current detected 0.. vdd2 over current not detected vdd2 uv : 1.. vdd2 under voltage detected 0.. vdd2 under voltage not detected vddcan uv : 1.. vddcan under voltage detected. if can is not activated, t his bit is high without generating a interrupt in this case. 0.. vddcan under voltage not detected vdd1 uv : 1.. vdd1 under voltage detected 0.. vdd1 under voltage not detected table 75: vdd1, vdd2 and vddcan status information. elmos semiconductor ag reserves the right to change the detail specifications as may be required to pe rmit improvements in the design of its products. elmos semiconductor ag data sheet qm-no.: 25ds0093e.0 1 70 / 82
can/lin sbc family with dc/dc voltage regulator e521 .02/03/04/12/13/14 production data ? mar 7, 2016 fig. 24: interrupt and status register dependency in case of interrupt detailed information can be re ad from device in order to evaluate reason for inte rrupt. elmos semiconductor ag reserves the right to change the detail specifications as may be required to pe rmit improvements in the design of its products. elmos semiconductor ag data sheet qm-no.: 25ds0093e.0 1 71 / 82
can/lin sbc family with dc/dc voltage regulator e521 .02/03/04/12/13/14 production data ? mar 7, 2016 5.10 dcdc buck converter; pins vin, vdd1, vdd1sense , lxt, pgnd register name address description vdd1_cfg 0x14 vdd1 configuration register writing register in sbc state failsafe is not allow ed table 76: vdd1 registertable register vdd1_cfg (0x14) msb lsb content t1_1 t1_0 idle - - stop thr_1 thr_0 reset value 0 1 1 0 0 0 0 0 access r/w r/w r/w r r r r/w r/w bit description t1_1 : configuration of time t1 for sbc mode stop obser vation t1_0 : configuration of time t1 for sbc mode stop obser vation 00...5ms 01...10ms 10...20ms 11...40ms idle : 1.. activate idle prevention 0.. deactivate idle prevention idle detected: ? dcdc on ? dcdc reports idle ? v(vdd1) < typ. 0.98*vdd1 nom stop : selection of behaviour in state stop 1..in case of high current consumption state remain s in stop 0..in case of high current consumption state is cha nged to normal thr_1 : selection of reset threshold thr_0 : selection of reset threshold 00...v th1,vdd1,rstn 01...v th2,vdd1,rstn 10...v th3,vdd1,rstn 11...v th4,vdd1,rstn table 77: vdd1 configuration register remark: register writing register in sbc state fail safe is not allowed elmos semiconductor ag reserves the right to change the detail specifications as may be required to pe rmit improvements in the design of its products. elmos semiconductor ag data sheet qm-no.: 25ds0093e.0 1 72 / 82
can/lin sbc family with dc/dc voltage regulator e521 .02/03/04/12/13/14 production data ? mar 7, 2016 5.10.1 general description the dcdc buck converter is a fixed output voltage s tep-down converter intended for automotive and gene ral bat- tery driven applications, featuring open loop stabi lity and short current limitation for the integrate d driver transistor. the device is offered in a 5v output voltage versio n providing up to 500ma output current. the modulation scheme is based on p ulse f requency m odulation. for operation a clock signal is not need ed, providing minimum on/off time regulation for the in ternal switch. internal current measurement allows to reduce the on time below the given nominal on time to prev ent excessive current flow in the inductor. 5.10.2 pulse frequency modulated converter the following sub chapters provide descriptions of the blocks implemented to control the output voltag e. the regu- lation principle provides an adaptive operation fre quency of typ. up to 1.3mhz, depending on v vin / v vdd1 voltage ratio and load conditions. pfm control logic pfm control logic generates the timings necessary t o control the converter based on a combination of o utput voltage, temperature and measured switch current. i t provides adaptive frequency, depending on input v oltage to output voltage ratio in the range of 0hz up to typ. >1.3mhz. internal power switch the internal highside power switch connects vin and lxt controlled by pfm control logic. the highside power switch current is limited provid ing saturation protection to the inductor and to pr event over cur- rent damage to the application. it allows startup o f the converter without soft-start measures. 5.10.3 application / implementation hints output voltage ripple is strongly dependent on peri pheral elements chosen (l lxt and c vdd1sense ) and their parasitic behavior. esr of output capacitance c vdd1sense must be suitable to ensure a small ripple for prop er regulation (see recommended operating conditions). the ripple volta ge can be calculated by v ripple,vdd1sense = r esr,cout * i ripple,l_lxt the dc resistance of l lxt reduces the efficiency but does not affect the out put voltage ripple. (though a high resist- ance can generate a significant thermal power withi n the inductor). furthermore higher dc resistance w ill also increase the minimum input voltage requirements for nominal output voltage. the free-wheeling diode must have a low forward vol tage as well as a low reverse recovery time. parasi tic capacit- ance of this diode decreases the overall efficiency and causes current spikes when the driver turns on (consider this behaviour for emi). for low power requirements on vdd1 consider the lea kage of the freewheeling diode at nominal converter output voltage. leakage current will contribute to the ove rall output current of the converter. a reverse polarity diode for vin is recommended. in emc sensitive environments additional decoupling m easures at vin are recommended. elmos semiconductor ag reserves the right to change the detail specifications as may be required to pe rmit improvements in the design of its products. elmos semiconductor ag data sheet qm-no.: 25ds0093e.0 1 73 / 82
can/lin sbc family with dc/dc voltage regulator e521 .02/03/04/12/13/14 production data ? mar 7, 2016 5.10.4 vdd1 under-voltage monitor if vdd1 < v thx,vdd1_f,rstn a reset is generated and pin rstn is set to l. sbc enters state restart or failsafe depending on sbc_cfg.cfg. if vdd1 > v thx,vdd1,rstn reset will be enlarged and rstn will be held l for t rstn,vdd1 . after that rstn is set to h. to prevent high or short current events vdd1 is monitored. if vdd1 < v thx,vdd1,rstn timeout t to,vdd1 is started. if timeout exceeds sbc is set to state failsafe and re gulator is switched off. if vdd1 > v thx,vdd1,rstn timeout is reset. timeout is enabled only if vs > v on-off,vs . otherwise vdd1 will not reach its output value. 5.11 low drop regulator; pins vdd2, envdd2 the on chip low drop voltage regulator (ldo) provid es a voltage of typically 5.0v at pin vdd2 . ldo can be active in sbc operating states normal, stop, sleep, restart o r failsafe. it can be activated via spi or via pin envdd2 . vs related pin envdd2 has higher priority. in order to save system curren t envdd2 does not implement pull down functionality. if the external pin envdd2 is low the spi register determines status of ldo. o therwise if the pin envdd2 is high the ldo is activated independently of the contents of the register vdd2_cfg.on. in case of external de activation of vdd2 using pin envdd2 ldo is switched off as well as spi register is rese t to off state. register vdd2_cfg can be written in state normal only. it is cleared in state failsafe. the ldo is limited in output cur rent. current limitation is always activated. over voltage protec tion against vs and reverse polarity protection are implemented. an over temperature protection using both warning a nd shutdown levels is implemented. in case of over temperat- ure detection an interrupt is generated. voltage su pervision including interrupt generation is impleme nted. register name address description vdd2_cfg 0x18 vdd2 configuration register table 78: vdd2 registertable register vdd2_cfg (0x18) msb lsb content - - - - - - - on reset value 0 0 0 0 0 0 0 0 access r r r r r r r r/w bit description on : 1... enables regulator table 79: vdd2 configuration register elmos semiconductor ag reserves the right to change the detail specifications as may be required to pe rmit improvements in the design of its products. elmos semiconductor ag data sheet qm-no.: 25ds0093e.0 1 74 / 82
can/lin sbc family with dc/dc voltage regulator e521 .02/03/04/12/13/14 production data ? mar 7, 2016 5.12 dcdc boost converter; pins mdrv, isen, pgnd2 for applications relevant during startup, an option al input voltage boost converter can be added. the boost con- verter activates if the supply voltage at pin vs fa lls below the v boost level. then the gate driver sets active level on pin mdrv driving the gate of external power-mos-swi tch for either maximum on-time t onmax4 or till the current reaches the threshold v isen sensing on shunt at pin isen. after switching off at pin mdrv the next switch on will be only after expiration minimum off-time t offmin4 . each switch on event holds the pin mdrv active at least for the minimum on-time t onmin4 regardless of current sense level at pin isen. so the boost converter is self oscillating. it can also be deactivated if pin isen is not connecte d to external rsense and externally pulled up betwe en 2v and vdd1 level. booster activation is controlled using sbc_cfg.boos t. in default setup booster set to off. fig. 25: functional diagram booster elmos semiconductor ag reserves the right to change the detail specifications as may be required to pe rmit improvements in the design of its products. elmos semiconductor ag data sheet qm-no.: 25ds0093e.0 1 75 / 82 vdd1 (nominal 5v) hsd l lsd vref1 v isen ga te c t r l level- shifter pf m vdd (nominal 3.3v) vref2 ++ - - lsup rsup supply parasitics v v rs e n s e extern fet i sense c boost_out c boost_in d1 d2 comp1 comp2 boost on if vdd1 > 4.5v & no por booster boost s option1 to suppress distortions caused by supply parasitics option2 d1
can/lin sbc family with dc/dc voltage regulator e521 .02/03/04/12/13/14 production data ? mar 7, 2016 6 register table register name address description sbc_cfg 0x01 sbc configuration register. fson_stat 0x02 fson status register. int 0x03 interrupt status register wu_src 0x04 wake up source register. wake up source is cleared if register is read. spi_fail 0x05 spi programming failure register. register is clear ed by reading via spi. lin_cfg 0x06 shortcut to lin1-4 tr and rc configuration bits wd_cfg 0x08 current watchdog configuration. change of configuration has to be performed using wd_cfg1 and wd_cfg2 including correct watchdo g trigger afterwards within one watchdog cycle in sbc mode normal wd_cfg1 0x09 watchdog configuration register 1 wd_cfg2 0x0a watchdog configuration register 2 wd_stat 0x0b watchdog status register wd_per 0x0c current watchdog period. change of period has to be performed using wd_per1 and wd_per2 including correct watchdog trig ger afterwards within one watchdog cycle. wd_trig 0x0d watchdog trigger register wd_per1 0x0e watchdog period register 1 wd_per2 0x0f watchdog period register 2. wk_cfg 0x10 configuration register of pin wk. register is writeable in sbc state normal only. in sbc states init, restart or failsafe all b its are set to h. vdd1_cfg 0x14 vdd1 configuration register. writing re gister in sbc state failsafe is not allowed vdd2_cfg 0x18 vdd2 configuration register vdd_stat 0x1a vdd1, vdd2 and vddcan status information. spi_stat 0x1b status register with respect to fsm. ot_stat 0x1f over temperature detection status register. lin1_cfg 0x20 configuration register for lin1 lin_int 0x21 lin interrupt register lin1_stat 0x22 status register for lin1 lin2_cfg 0x24 configuration register for lin2 lin2_stat 0x26 status register for lin2 lin3_cfg 0x28 configuration register for lin3 lin3_stat 0x2a status register for lin3 lin4_cfg 0x2c configuration register for lin4 lin4_stat 0x2e status register for lin4 can_cfg 0x30 configuration register for can can_stat 0x32 status register for can table 80: register table elmos semiconductor ag reserves the right to change the detail specifications as may be required to pe rmit improvements in the design of its products. elmos semiconductor ag data sheet qm-no.: 25ds0093e.0 1 76 / 82
can/lin sbc family with dc/dc voltage regulator e521 .02/03/04/12/13/14 production data ? mar 7, 2016 7 applications information 7.1 overview the device e521.02 .. e521.04 is used in applicatio n without pre-booster, while e521.12 .. e521.14 sup ports pre- boost functionality. the following chapters show ty pical operating circuits of these two use cases. 7.2 typical operating circuit with booster table 81. external components description condition symbol min typ max unit battery supply input pins battery filter capacitor to ground c 1 100 nf battery buffer capacitor to ground c 2 47 f emc filter inductor saturation current relative to maximum application current i vdd1 l 1 2.2 h elmos semiconductor ag reserves the right to change the detail specifications as may be required to pe rmit improvements in the design of its products. elmos semiconductor ag data sheet qm-no.: 25ds0093e.0 1 77 / 82
can/lin sbc family with dc/dc voltage regulator e521 .02/03/04/12/13/14 production data ? mar 7, 2016 description condition symbol min typ max unit vs, vin buffer capacitance to ground effective esr o f c 3 , c 4 shall be < 300m c 3 10 22 - f vs, vin filter capacitance to ground effective esr o f c 3 , c 4 shall be < 300m c 4 100 nf wk optional lp filter capacitance for wk c wk 22 nf lp filter resistor for pin wk r wk 1 3.3 10 k vdd1 inductance at lxt to output voltage i vdd1 < 500ma l 2 18 33 82 h serial resistance of lxt inductance i vdd1 < 500ma r l2 0.1 0.6 relative saturation current of lxt inductor saturation current relative to maximum application current i vdd1 i l2,sat 130 % freewheeling diode forward voltage e.g. mbr forward current 1.3 x i(vdd1) t amb = 25c v d2 0.6 1 v reverse recovery time of freewheel- ing diode forward current 1.3 x i(vdd1) t amb = 25c t d2,rec 10 25 ns peak to peak voltage ripple at vdd1sense for regulation, regulation ripple included in 2% toler- ance window for vdd1 v vdd1sense,ripp le 10 100 mv vdd1sense decoupling resistor r ser 50 60 140 m vdd1_1 external buffer capacitor effective esr of c 5 , c 6 , c 7 , c 8 shall be < 10m c 5 10 f vdd1_1 external filter capacitor effective esr of c 5 , c 6 , c 7 , c 8 shall be < 10m c 6 33 nf vdd1_2 external buffer capacitor effective esr of c 5 , c 6 , c 7 , c 8 shall be < 10m c 7 10 f vdd1_2 external filter capacitor effective esr of c 5 , c 6 , c 7 , c 8 shall be < 10m c 8 33 nf vddcan vddcan external buffer capacitor esr < tbd c 9 10 f vddcan external filter capacitor esr < tbd c 10 33 nf elmos semiconductor ag reserves the right to change the detail specifications as may be required to pe rmit improvements in the design of its products. elmos semiconductor ag data sheet qm-no.: 25ds0093e.0 1 78 / 82
can/lin sbc family with dc/dc voltage regulator e521 .02/03/04/12/13/14 production data ? mar 7, 2016 description condition symbol min typ max unit vdd2 external buffer capacitor for vdd2 esr > 200m c 11 2.2 22 f external filter capacitor close to pin vdd2 c 12 100 nf external filter capacitor close to external connector if used as external sensor sup- ply (global pin) c 13 4.7 nf booster (optional) booster inductance i sat depends on r sense selection l 1 2.2 h booster diode, e.g. ss24 d 2 booster input buffer capacitance c 2 50 100 - f booster input filter capacitance c 1 tbd nf booster output buffer capacitance i load_vs < 600ma esr < 50m c 3 50 - f booster output filter capacitance c 4 tbd nf current sense resistance i sat_lboost > 1.8a r 1_60 60 m current sense resistance i sat_lboost > 3.6a r 1_30 30 m rdson of the external fet v vdd1 > 4.5v r dson,t1 30 m total gate charge of the external fet v ds = 5v v gs = 5v i d = 3.6a v th < 3v qb boost_ext_fet 10 nc maximal forward current of the external booster diode d1, d2 i av(skd_boost) 3.6 a maximal forward voltage of the external booster diode d1, d2 @ 3.6a v f(skd_boost) 500 mv elmos semiconductor ag reserves the right to change the detail specifications as may be required to pe rmit improvements in the design of its products. elmos semiconductor ag data sheet qm-no.: 25ds0093e.0 1 79 / 82
can/lin sbc family with dc/dc voltage regulator e521 .02/03/04/12/13/14 production data ? mar 7, 2016 8 package information the e521.14 device family is available in a pb free , rohs compliant, qfn44l7 plastic package according to jedec mo-220 k.01 vkkd-3. the package is classified to moisture sensitivity l evel 3 (msl 3) according to jedec j-std-020c with a soldering peak temperature of (260+5)c. note: thermal resistance junction to ambient r th,ja is typ. 24 c/w, based on jedec standard jesd-51-2 , jesd- 51-5 and jesd-51-7. description symbol mm inch min typ max min typ max package height a 0.80 0.90 1.00 0.031 0.035 0.039 stand off a1 0.00 0.02 0.05 0.000 0.00079 0.002 thickness of terminal leads, including lead finish a3 -- 0.20 ref -- -- 0.0079 ref -- width of terminal leads b 0.18 0.25 0.30 0.007 0.010 0.012 package length / width d / e -- 7.00 bsc -- -- 0.276 bsc -- length / width of exposed pad d2 / e2 5.50 5.65 5.80 0.217 0.223 0.229 lead pitch e -- 0.5 bsc -- -- 0.020 bsc -- length of terminal for soldering to substrate l 0.35 0 .40 0.45 0.014 0.016 0.018 number of terminal positions n 44 44 note: the mm values are valid, the inch values contains rounding errors elmos semiconductor ag reserves the right to change the detail specifications as may be required to pe rmit improvements in the design of its products. elmos semiconductor ag data sheet qm-no.: 25ds0093e.0 1 80 / 82
can/lin sbc family with dc/dc voltage regulator e521 .02/03/04/12/13/14 production data ? mar 7, 2016 elmos semiconductor ag reserves the right to change the detail specifications as may be required to pe rmit improvements in the design of its products. elmos semiconductor ag data sheet qm-no.: 25ds0093e.0 1 81 / 82 warning ? life support applications policy elmos semiconductor ag is continually working to improve th e quality and reliability of its products. nevertheless, se miconductor devices in general can malfunction or fail due to their inherent electr ical sensitivity and vulnerability to physical stress. it i s the responsibility of the buyer, when utilizing elmos semiconductor ag products, to observe standards of safety, and to avoid situations in which malfun ction or failure of an elmos semiconductor ag product could cause loss of human lif e, body injury or damage to property. in development your des igns, please ensure that elmos semiconductor ag products are used within specified operating ranges as set forth in the most recent pr oduct specifica- tions. general disclaimer information furnished by elmos semiconductor ag is believe d to be accurate and reliable. however, no responsibility is assumed by elmos semiconductor ag for its use, nor for any infringements of pa tents or other rights of third parties, which may result from its use. no license is granted by implication or otherwise under any patent or pate nt rights of elmos semiconductor ag. elmos semiconductor ag reserves the right to make changes to this document or the products contained th erein without prior notice, to improve performance, reliab ility, or manufacturabil- ity . application disclaimer circuit diagrams may contain components not manufactured b y elmos semiconductor ag, which are included as means of illu strating typical applications. consequently, complete information suffic ient for construction purposes is not necessarily given. th e information in the applica- tion examples has been carefully checked and is believed to b e entirely reliable. however, no responsibility is assumed for inaccuracies. fur- thermore, such information does not convey to the purchaser of the semiconductor devices described any license under th e patent rights of elmos semiconductor ag or others.
can/lin sbc family with dc/dc voltage regulator e521 .02/03/04/12/13/14 production data ? mar 7, 2016 elmos semiconductor ag reserves the right to change the detail specifications as may be required to pe rmit improvements in the design of its products. elmos semiconductor ag data sheet qm-no.: 25ds0093e.0 1 82 / 82 contact information headquarters elmos semiconductor ag heinrich-hertz-str. 1 ? d-44227 dortmund (germany) Y : +492317549100 : sales-germany@elmos.com : www.elmos.com sales and application support office north america elmos na. inc. 32255 northwestern highway ? suite 220 farmington h ills mi 48334 (usa) Y : +12488653200 : sales-usa@elmos.com sales and application support office china elmos semiconductor technology (shanghai) co., ltd. unit 16b, 16f zhao feng world trade building, no. 369 jiang su road, chang ning district, shanghai, pr china, 200050 Y : +86216210 0908 : sales-china@elmos.com sales and application support office korea elmos korea b-1007, u-space 2, #670 daewangpangyo-ro, sampyoung-dong, bunddang-gu, sungnam-si kyounggi-do 463-400 korea Y : +82317141131 : sales-korea@elmos.com sales and application support office japan elmos japan k.k. br shibaura n bldg. 7f 3-20-9 shibaura, minato-ku, tokyo 108-0023 japan Y : +81334517101 : sales-japan@elmos.com sales and application support office singapore elmos semiconductor singapore pte ltd. 3a international business park #09-13 icon@ibp ? 609935 singapore Y : +65 6908 1261 : sales-singapore@elmos.com ? elmos semiconductor ag, 2016. reproduction, in part or whole, without the prior written consent of elmos semiconductor ag, is proh ibited.

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